2 * Copyright (C) 2011 Renesas Solutions Corp.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_CPU_SH7757_H_
8 #define _ASM_CPU_SH7757_H_
10 #define CCR 0xFF00001C
11 #define WTCNT 0xFFCC0000
12 #define CCR_CACHE_INIT 0x0000090b
13 #define CACHE_OC_NUM_WAYS 1
15 #ifndef __ASSEMBLY__ /* put C only stuff in this section */
18 unsigned int reserved[4];
21 #define MMU_BASE ((struct mmu_regs *)0xff000000)
24 #define WTCSR0 0xffcc0002
25 #define WRSTCSR_R 0xffcc0003
26 #define WRSTCSR_W 0xffcc0002
27 #define WTCSR_PREFIX 0xa500
28 #define WRSTCSR_PREFIX 0x6900
29 #define WRSTCSR_WOVF_PREFIX 0x9600
32 #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
33 #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
34 #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
37 #define SMR0 0xfe470000
40 #define TMU_BASE 0xFE430000
42 /* ETHER, GETHER MAC address */
43 struct ether_mac_regs {
44 unsigned int reserved[114];
46 unsigned int reserved2;
49 #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
50 #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
51 #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
52 #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
55 struct gether_control_regs {
58 #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
59 #define GBECONT_RMII1 0x00020000
60 #define GBECONT_RMII0 0x00010000
63 struct usb_common_regs {
64 unsigned short reserved[129];
65 unsigned short suspmode;
67 #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
68 #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
70 struct usb0_phy_regs {
72 unsigned short reserved[4];
73 unsigned short portsel;
75 #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
77 struct usb1_port_regs {
78 unsigned int port1sel;
79 unsigned int reserved;
80 unsigned int usb1intsts;
82 #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
84 struct usb1_alignment_regs {
85 unsigned int ehcidatac; /* 0xfe4fe018 */
86 unsigned int reserved[63];
87 unsigned int ohcidatac;
89 #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
93 unsigned int wprotect;
95 unsigned int gracr2; /* GRA */
96 unsigned int gracr3; /* GRA */
97 unsigned int reserved[4];
100 unsigned int reserved2[2];
101 unsigned int gpll1div;
102 unsigned int vcompsel;
103 unsigned int reserved3[62];
105 unsigned int reserved4[2];
106 unsigned int flcrmon;
107 unsigned int reserved5[944];
108 unsigned int spibootcan;
110 #define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
113 struct pcie_setup_regs {
114 unsigned int pbictl0;
115 unsigned int gradevctl;
116 unsigned int reserved[2];
117 unsigned int bmcinf[6];
118 unsigned int reserved2[118];
119 unsigned int idset[2];
120 unsigned int subidset;
121 unsigned int reserved3[2];
122 unsigned int linkconfset[4];
124 unsigned int reserved4[6];
125 unsigned int toutset;
126 unsigned int reserved5[7];
128 unsigned int ladmsk0;
130 unsigned int ladmsk1;
132 unsigned int ladmsk2;
134 unsigned int ladmsk3;
136 unsigned int ladmsk4;
138 unsigned int ladmsk5;
139 unsigned int reserved6[94];
140 unsigned int vdmrxvid[2];
141 unsigned int reserved7;
142 unsigned int pbiintfr;
143 unsigned int pbiinten;
146 unsigned int baracsize;
147 unsigned int advserest;
148 unsigned int pbictl3;
149 unsigned int reserved8[8];
150 unsigned int pbictl1;
151 unsigned int scratch0;
152 unsigned int reserved9[6];
153 unsigned int pbictl2;
154 unsigned int reserved10;
157 #define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
159 struct pcie_system_bus_regs {
160 unsigned int reserved[3];
161 unsigned int endictl0;
162 unsigned int endictl1;
164 #define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
168 struct pciebrg_regs {
169 unsigned short ctrl_h8s;
170 unsigned short reserved[7];
171 unsigned short cp_addr;
172 unsigned short reserved2;
173 unsigned short cp_data;
174 unsigned short reserved3;
175 unsigned short cp_ctrl;
177 #define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
180 #define CCN_PRR 0xff000044
181 #define prr_mask(_val) ((_val >> 4) & 0xff)
182 #define PRR_SH7757_B0 0x10
183 #define PRR_SH7757_C0 0x11
185 #define is_sh7757_b0(_val) \
187 int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
190 #endif /* ifndef __ASSEMBLY__ */
192 #endif /* _ASM_CPU_SH7757_H_ */