1 #ifndef __ASM_SH_CACHE_H
2 #define __ASM_SH_CACHE_H
4 #if defined(CONFIG_CPU_SH4)
6 #define L1_CACHE_BYTES 32
8 struct __large_struct { unsigned long buf[100]; };
9 #define __m(x) (*(struct __large_struct *)(x))
14 * 32-bytes is the largest L1 data cache line size for SH the architecture. So
15 * it is a safe default for DMA alignment.
17 #define ARCH_DMA_MINALIGN 32
19 #endif /* CONFIG_CPU_SH4 */
22 * Use the L1 data cache line size value for the minimum DMA buffer alignment
25 #ifndef ARCH_DMA_MINALIGN
26 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
29 #endif /* __ASM_SH_CACHE_H */