arch/riscv/lib/andes_plic.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019, Rick Chen <rick@andestech.com>
   4  *
   5  * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
   6  * The PLIC block holds memory-mapped claim and pending registers
   7  * associated with software interrupt.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass-internal.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/syscon.h>
  19 #include <cpu.h>
  20 #include <linux/err.h>
  21
  22 /* pending register */
  23 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
  24 /* enable register */
  25 #define ENABLE_REG(base, hart)  ((ulong)(base) + 0x2000 + (hart) * 0x80)
  26 /* claim register */
  27 #define CLAIM_REG(base, hart)   ((ulong)(base) + 0x200004 + (hart) * 0x1000)
  28
  29 #define ENABLE_HART_IPI         (0x80808080)
  30 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33 static int init_plic(void);
  34
  35 #define PLIC_BASE_GET(void)                                             \
  36         do {                                                            \
  37                 long *ret;                                              \
  38                                                                         \
  39                 if (!gd->arch.plic) {                                   \
  40                         ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
  41                         if (IS_ERR(ret))                                \
  42                                 return PTR_ERR(ret);                    \
  43                         gd->arch.plic = ret;                            \
  44                         init_plic();                                    \
  45                 }                                                       \
  46         } while (0)
  47
  48 static int enable_ipi(int hart)
  49 {
  50         unsigned int en;
  51
  52         en = ENABLE_HART_IPI >> hart;
  53         writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
  54
  55         return 0;
  56 }
  57
  58 static int init_plic(void)
  59 {
  60         struct udevice *dev;
  61         ofnode node;
  62         int ret;
  63         u32 reg;
  64
  65         ret = uclass_find_first_device(UCLASS_CPU, &dev);
  66         if (ret)
  67                 return ret;
  68
  69         if (ret == 0 && dev) {
  70                 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  71                         const char *device_type;
  72
  73                         device_type = ofnode_read_string(node, "device_type");
  74                         if (!device_type)
  75                                 continue;
  76
  77                         if (strcmp(device_type, "cpu"))
  78                                 continue;
  79
  80                         /* skip if hart is marked as not available */
  81                         if (!ofnode_is_available(node))
  82                                 continue;
  83
  84                         /* read hart ID of CPU */
  85                         ret = ofnode_read_u32(node, "reg", &reg);
  86                         if (ret == 0)
  87                                 enable_ipi(reg);
  88                 }
  89
  90                 return 0;
  91         }
  92
  93         return -ENODEV;
  94 }
  95
  96 int riscv_send_ipi(int hart)
  97 {
  98         unsigned int ipi;
  99
 100         PLIC_BASE_GET();
 101
 102         ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 103         writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
 104                                 gd->arch.boot_hart));
 105
 106         return 0;
 107 }
 108
 109 int riscv_clear_ipi(int hart)
 110 {
 111         u32 source_id;
 112
 113         PLIC_BASE_GET();
 114
 115         source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 116         writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 117
 118         return 0;
 119 }
 120
 121 int riscv_get_ipi(int hart, int *pending)
 122 {
 123         PLIC_BASE_GET();
 124
 125         *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
 126                                                      gd->arch.boot_hart));
 127         *pending = !!(*pending & SEND_IPI_TO_HART(hart));
 128
 129         return 0;
 130 }
 131
 132 static const struct udevice_id andes_plic_ids[] = {
 133         { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
 134         { }
 135 };
 136
 137 U_BOOT_DRIVER(andes_plic) = {
 138         .name           = "andes_plic",
 139         .id             = UCLASS_SYSCON,
 140         .of_match       = andes_plic_ids,
 141         .flags          = DM_FLAG_PRE_RELOC,
 142 };