1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2017 Microsemi Corporation.
4 * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
7 #ifndef RISCV_CSR_ENCODING_H
8 #define RISCV_CSR_ENCODING_H
12 #if CONFIG_IS_ENABLED(RISCV_SMODE)
13 #define MODE_PREFIX(__suffix) s##__suffix
15 #define MODE_PREFIX(__suffix) m##__suffix
18 #define MSTATUS_UIE 0x00000001
19 #define MSTATUS_SIE 0x00000002
20 #define MSTATUS_HIE 0x00000004
21 #define MSTATUS_MIE 0x00000008
22 #define MSTATUS_UPIE 0x00000010
23 #define MSTATUS_SPIE 0x00000020
24 #define MSTATUS_HPIE 0x00000040
25 #define MSTATUS_MPIE 0x00000080
26 #define MSTATUS_SPP 0x00000100
27 #define MSTATUS_HPP 0x00000600
28 #define MSTATUS_MPP 0x00001800
29 #define MSTATUS_FS 0x00006000
30 #define MSTATUS_XS 0x00018000
31 #define MSTATUS_MPRV 0x00020000
32 #define MSTATUS_PUM 0x00040000
33 #define MSTATUS_VM 0x1F000000
34 #define MSTATUS32_SD 0x80000000
35 #define MSTATUS64_SD 0x8000000000000000
37 #define MCAUSE32_CAUSE 0x7FFFFFFF
38 #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
39 #define MCAUSE32_INT 0x80000000
40 #define MCAUSE64_INT 0x8000000000000000
42 #define SSTATUS_UIE 0x00000001
43 #define SSTATUS_SIE 0x00000002
44 #define SSTATUS_UPIE 0x00000010
45 #define SSTATUS_SPIE 0x00000020
46 #define SSTATUS_SPP 0x00000100
47 #define SSTATUS_FS 0x00006000
48 #define SSTATUS_XS 0x00018000
49 #define SSTATUS_PUM 0x00040000
50 #define SSTATUS32_SD 0x80000000
51 #define SSTATUS64_SD 0x8000000000000000
53 #define MIP_SSIP BIT(IRQ_S_SOFT)
54 #define MIP_MSIP BIT(IRQ_M_SOFT)
55 #define MIP_STIP BIT(IRQ_S_TIMER)
56 #define MIP_MTIP BIT(IRQ_M_TIMER)
57 #define MIP_SEIP BIT(IRQ_S_EXT)
58 #define MIP_MEIP BIT(IRQ_M_EXT)
60 #define SIP_SSIP MIP_SSIP
61 #define SIP_STIP MIP_STIP
75 #define CAUSE_MISALIGNED_FETCH 0
76 #define CAUSE_FETCH_ACCESS 1
77 #define CAUSE_ILLEGAL_INSTRUCTION 2
78 #define CAUSE_BREAKPOINT 3
79 #define CAUSE_MISALIGNED_LOAD 4
80 #define CAUSE_LOAD_ACCESS 5
81 #define CAUSE_MISALIGNED_STORE 6
82 #define CAUSE_STORE_ACCESS 7
83 #define CAUSE_USER_ECALL 8
84 #define CAUSE_SUPERVISOR_ECALL 9
85 #define CAUSE_MACHINE_ECALL 11
86 #define CAUSE_FETCH_PAGE_FAULT 12
87 #define CAUSE_LOAD_PAGE_FAULT 13
88 #define CAUSE_STORE_PAGE_FAULT 15
90 #define DEFAULT_RSTVEC 0x00001000
91 #define DEFAULT_NMIVEC 0x00001004
92 #define DEFAULT_MTVEC 0x00001010
93 #define CONFIG_STRING_ADDR 0x0000100C
94 #define EXT_IO_BASE 0x40000000
95 #define DRAM_BASE 0x80000000
97 // page table entry (PTE) fields
98 #define PTE_V 0x001 // Valid
99 #define PTE_TYPE 0x01E // Type
100 #define PTE_R 0x020 // Referenced
101 #define PTE_D 0x040 // Dirty
102 #define PTE_SOFT 0x380 // Reserved for Software
104 #define PTE_TYPE_TABLE 0x00
105 #define PTE_TYPE_TABLE_GLOBAL 0x02
106 #define PTE_TYPE_URX_SR 0x04
107 #define PTE_TYPE_URWX_SRW 0x06
108 #define PTE_TYPE_UR_SR 0x08
109 #define PTE_TYPE_URW_SRW 0x0A
110 #define PTE_TYPE_URX_SRX 0x0C
111 #define PTE_TYPE_URWX_SRWX0x0E
112 #define PTE_TYPE_SR 0x10
113 #define PTE_TYPE_SRW 0x12
114 #define PTE_TYPE_SRX 0x14
115 #define PTE_TYPE_SRWX 0x16
116 #define PTE_TYPE_SR_GLOBAL 0x18
117 #define PTE_TYPE_SRW_GLOBAL 0x1A
118 #define PTE_TYPE_SRX_GLOBAL 0x1C
119 #define PTE_TYPE_SRWX_GLOBAL 0x1E
121 #define PTE_PPN_SHIFT 10
123 #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
124 #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
125 #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
126 #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
127 #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
128 #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
129 #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
131 #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
132 typeof(_PTE) (PTE) = (_PTE); \
133 typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
134 ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
135 (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
136 ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
141 # define MSTATUS_SD MSTATUS64_SD
142 # define SSTATUS_SD SSTATUS64_SD
143 # define MCAUSE_INT MCAUSE64_INT
144 # define MCAUSE_CAUSE MCAUSE64_CAUSE
145 # define RISCV_PGLEVEL_BITS 9
147 # define MSTATUS_SD MSTATUS32_SD
148 # define SSTATUS_SD SSTATUS32_SD
149 # define RISCV_PGLEVEL_BITS 10
150 # define MCAUSE_INT MCAUSE32_INT
151 # define MCAUSE_CAUSE MCAUSE32_CAUSE
154 #define RISCV_PGSHIFT 12
155 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
159 #endif /* RISCV_CSR_ENCODING_H */