1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2017 Microsemi Corporation.
4 * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
7 #ifndef RISCV_CSR_ENCODING_H
8 #define RISCV_CSR_ENCODING_H
10 #ifdef CONFIG_RISCV_SMODE
11 #define MODE_PREFIX(__suffix) s##__suffix
13 #define MODE_PREFIX(__suffix) m##__suffix
16 #define MSTATUS_UIE 0x00000001
17 #define MSTATUS_SIE 0x00000002
18 #define MSTATUS_HIE 0x00000004
19 #define MSTATUS_MIE 0x00000008
20 #define MSTATUS_UPIE 0x00000010
21 #define MSTATUS_SPIE 0x00000020
22 #define MSTATUS_HPIE 0x00000040
23 #define MSTATUS_MPIE 0x00000080
24 #define MSTATUS_SPP 0x00000100
25 #define MSTATUS_HPP 0x00000600
26 #define MSTATUS_MPP 0x00001800
27 #define MSTATUS_FS 0x00006000
28 #define MSTATUS_XS 0x00018000
29 #define MSTATUS_MPRV 0x00020000
30 #define MSTATUS_PUM 0x00040000
31 #define MSTATUS_VM 0x1F000000
32 #define MSTATUS32_SD 0x80000000
33 #define MSTATUS64_SD 0x8000000000000000
35 #define MCAUSE32_CAUSE 0x7FFFFFFF
36 #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
37 #define MCAUSE32_INT 0x80000000
38 #define MCAUSE64_INT 0x8000000000000000
40 #define SSTATUS_UIE 0x00000001
41 #define SSTATUS_SIE 0x00000002
42 #define SSTATUS_UPIE 0x00000010
43 #define SSTATUS_SPIE 0x00000020
44 #define SSTATUS_SPP 0x00000100
45 #define SSTATUS_FS 0x00006000
46 #define SSTATUS_XS 0x00018000
47 #define SSTATUS_PUM 0x00040000
48 #define SSTATUS32_SD 0x80000000
49 #define SSTATUS64_SD 0x8000000000000000
51 #define MIP_SSIP BIT(IRQ_S_SOFT)
52 #define MIP_HSIP BIT(IRQ_H_SOFT)
53 #define MIP_MSIP BIT(IRQ_M_SOFT)
54 #define MIP_STIP BIT(IRQ_S_TIMER)
55 #define MIP_HTIP BIT(IRQ_H_TIMER)
56 #define MIP_MTIP BIT(IRQ_M_TIMER)
57 #define MIP_SEIP BIT(IRQ_S_EXT)
58 #define MIP_HEIP BIT(IRQ_H_EXT)
59 #define MIP_MEIP BIT(IRQ_M_EXT)
61 #define SIP_SSIP MIP_SSIP
62 #define SIP_STIP MIP_STIP
88 #define DEFAULT_RSTVEC 0x00001000
89 #define DEFAULT_NMIVEC 0x00001004
90 #define DEFAULT_MTVEC 0x00001010
91 #define CONFIG_STRING_ADDR 0x0000100C
92 #define EXT_IO_BASE 0x40000000
93 #define DRAM_BASE 0x80000000
95 // page table entry (PTE) fields
96 #define PTE_V 0x001 // Valid
97 #define PTE_TYPE 0x01E // Type
98 #define PTE_R 0x020 // Referenced
99 #define PTE_D 0x040 // Dirty
100 #define PTE_SOFT 0x380 // Reserved for Software
102 #define PTE_TYPE_TABLE 0x00
103 #define PTE_TYPE_TABLE_GLOBAL 0x02
104 #define PTE_TYPE_URX_SR 0x04
105 #define PTE_TYPE_URWX_SRW 0x06
106 #define PTE_TYPE_UR_SR 0x08
107 #define PTE_TYPE_URW_SRW 0x0A
108 #define PTE_TYPE_URX_SRX 0x0C
109 #define PTE_TYPE_URWX_SRWX0x0E
110 #define PTE_TYPE_SR 0x10
111 #define PTE_TYPE_SRW 0x12
112 #define PTE_TYPE_SRX 0x14
113 #define PTE_TYPE_SRWX 0x16
114 #define PTE_TYPE_SR_GLOBAL 0x18
115 #define PTE_TYPE_SRW_GLOBAL 0x1A
116 #define PTE_TYPE_SRX_GLOBAL 0x1C
117 #define PTE_TYPE_SRWX_GLOBAL 0x1E
119 #define PTE_PPN_SHIFT 10
121 #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
122 #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
123 #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
124 #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
125 #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
126 #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
127 #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
129 #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
130 typeof(_PTE) (PTE) = (_PTE); \
131 typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
132 ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
133 (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
134 ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
139 # define MSTATUS_SD MSTATUS64_SD
140 # define SSTATUS_SD SSTATUS64_SD
141 # define MCAUSE_INT MCAUSE64_INT
142 # define MCAUSE_CAUSE MCAUSE64_CAUSE
143 # define RISCV_PGLEVEL_BITS 9
145 # define MSTATUS_SD MSTATUS32_SD
146 # define SSTATUS_SD SSTATUS32_SD
147 # define RISCV_PGLEVEL_BITS 10
148 # define MCAUSE_INT MCAUSE32_INT
149 # define MCAUSE_CAUSE MCAUSE32_CAUSE
152 #define RISCV_PGSHIFT 12
153 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
157 #endif /* RISCV_CSR_ENCODING_H */