arch/riscv/dts/fu540-c000-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * (C) Copyright 2019 SiFive, Inc
   4  */
   5
   6 / {
   7         cpus {
   8                 assigned-clocks = <&prci PRCI_CLK_COREPLL>;
   9                 assigned-clock-rates = <1000000000>;
  10                 u-boot,dm-spl;
  11                 cpu0: cpu@0 {
  12                         clocks = <&prci PRCI_CLK_COREPLL>;
  13                         u-boot,dm-spl;
  14                         status = "okay";
  15                         cpu0_intc: interrupt-controller {
  16                                 u-boot,dm-spl;
  17                         };
  18                 };
  19                 cpu1: cpu@1 {
  20                         clocks = <&prci PRCI_CLK_COREPLL>;
  21                         u-boot,dm-spl;
  22                         cpu1_intc: interrupt-controller {
  23                                 u-boot,dm-spl;
  24                         };
  25                 };
  26                 cpu2: cpu@2 {
  27                         clocks = <&prci PRCI_CLK_COREPLL>;
  28                         u-boot,dm-spl;
  29                         cpu2_intc: interrupt-controller {
  30                                  u-boot,dm-spl;
  31                         };
  32                 };
  33                 cpu3: cpu@3 {
  34                         clocks = <&prci PRCI_CLK_COREPLL>;
  35                         u-boot,dm-spl;
  36                         cpu3_intc: interrupt-controller {
  37                                 u-boot,dm-spl;
  38                         };
  39                 };
  40                 cpu4: cpu@4 {
  41                         clocks = <&prci PRCI_CLK_COREPLL>;
  42                         u-boot,dm-spl;
  43                         cpu4_intc: interrupt-controller {
  44                                 u-boot,dm-spl;
  45                         };
  46                 };
  47         };
  48
  49         soc {
  50                 u-boot,dm-spl;
  51                 otp: otp@10070000 {
  52                         compatible = "sifive,fu540-c000-otp";
  53                         reg = <0x0 0x10070000 0x0 0x0FFF>;
  54                         fuse-count = <0x1000>;
  55                 };
  56                 clint@2000000 {
  57                         compatible = "riscv,clint0";
  58                         interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
  59                         reg = <0x0 0x2000000 0x0 0xc0000>;
  60                         u-boot,dm-spl;
  61                 };
  62                 dmc: dmc@100b0000 {
  63                         compatible = "sifive,fu540-c000-ddr";
  64                         reg = <0x0 0x100b0000 0x0 0x0800
  65                                0x0 0x100b2000 0x0 0x2000
  66                                0x0 0x100b8000 0x0 0x0fff>;
  67                         clocks = <&prci PRCI_CLK_DDRPLL>;
  68                         clock-frequency = <933333324>;
  69                         u-boot,dm-spl;
  70                 };
  71         };
  72 };
  73
  74 &prci {
  75         u-boot,dm-spl;
  76 };
  77
  78 &uart0 {
  79         u-boot,dm-spl;
  80 };
  81
  82 &qspi2 {
  83         u-boot,dm-spl;
  84 };
  85
  86 &eth0 {
  87         assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
  88         assigned-clock-rates = <125000000>;
  89 };