6 compatible = "andestech,ax25";
7 model = "andestech,ax25";
15 bootargs = "console=ttyS0,38400n8 debug loglevel=7";
16 stdout-path = "uart0:38400n8";
22 timebase-frequency = <60000000>;
28 riscv,isa = "rv64imafdc";
29 riscv,priv-major = <1>;
30 riscv,priv-minor = <10>;
31 mmu-type = "riscv,sv39";
32 clock-frequency = <60000000>;
33 i-cache-size = <0x8000>;
34 i-cache-line-size = <32>;
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <32>;
37 next-level-cache = <&L2>;
38 CPU0_intc: interrupt-controller {
39 #interrupt-cells = <1>;
41 compatible = "riscv,cpu-intc";
49 riscv,isa = "rv64imafdc";
50 riscv,priv-major = <1>;
51 riscv,priv-minor = <10>;
52 mmu-type = "riscv,sv39";
53 clock-frequency = <60000000>;
54 i-cache-size = <0x8000>;
55 i-cache-line-size = <32>;
56 d-cache-size = <0x8000>;
57 d-cache-line-size = <32>;
58 next-level-cache = <&L2>;
59 CPU1_intc: interrupt-controller {
60 #interrupt-cells = <1>;
62 compatible = "riscv,cpu-intc";
66 L2: l2-cache@e0500000 {
69 cache-size = <0x40000>;
70 reg = <0x0 0xe0500000 0x0 0x40000>;
75 device_type = "memory";
76 reg = <0x0 0x00000000 0x0 0x40000000>;
82 compatible = "simple-bus";
85 plic0: interrupt-controller@e4000000 {
86 compatible = "riscv,plic0";
88 #interrupt-cells = <2>;
90 reg = <0x0 0xe4000000 0x0 0x2000000>;
92 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
95 plic1: interrupt-controller@e6400000 {
96 compatible = "riscv,plic1";
98 #interrupt-cells = <2>;
100 reg = <0x0 0xe6400000 0x0 0x400000>;
102 interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
106 compatible = "riscv,plmt0";
107 interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
108 reg = <0x0 0xe6000000 0x0 0x100000>;
112 spiclk: virt_100mhz {
114 compatible = "fixed-clock";
115 clock-frequency = <100000000>;
118 timer0: timer@f0400000 {
119 compatible = "andestech,atcpit100";
120 reg = <0x0 0xf0400000 0x0 0x1000>;
121 clock-frequency = <60000000>;
123 interrupt-parent = <&plic0>;
126 serial0: serial@f0300000 {
127 compatible = "andestech,uart16550", "ns16550a";
128 reg = <0x0 0xf0300000 0x0 0x1000>;
130 clock-frequency = <19660800>;
133 no-loopback-test = <1>;
134 interrupt-parent = <&plic0>;
138 compatible = "andestech,atmac100";
139 reg = <0x0 0xe0100000 0x0 0x1000>;
141 interrupt-parent = <&plic0>;
145 compatible = "andestech,atfsdc010";
146 max-frequency = <100000000>;
147 clock-freq-min-max = <400000 100000000>;
149 reg = <0x0 0xf0e00000 0x0 0x1000>;
152 interrupt-parent = <&plic0>;
156 compatible = "andestech,atcdmac300";
157 reg = <0x0 0xf0c00000 0x0 0x1000>;
158 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
160 interrupt-parent = <&plic0>;
164 compatible = "andestech,atflcdc100";
165 reg = <0x0 0xe0200000 0x0 0x1000>;
167 interrupt-parent = <&plic0>;
171 compatible = "andestech,atfsmc020";
172 reg = <0x0 0xe0400000 0x0 0x1000>;
176 compatible = "andestech,atfac97";
177 reg = <0x0 0xf0d00000 0x0 0x1000>;
179 interrupt-parent = <&plic0>;
183 compatible = "riscv,base-pmu";
186 virtio_mmio@fe007000 {
187 interrupts = <0x17 0x4>;
188 interrupt-parent = <0x2>;
189 reg = <0x0 0xfe007000 0x0 0x1000>;
190 compatible = "virtio,mmio";
193 virtio_mmio@fe006000 {
194 interrupts = <0x16 0x4>;
195 interrupt-parent = <0x2>;
196 reg = <0x0 0xfe006000 0x0 0x1000>;
197 compatible = "virtio,mmio";
200 virtio_mmio@fe005000 {
201 interrupts = <0x15 0x4>;
202 interrupt-parent = <0x2>;
203 reg = <0x0 0xfe005000 0x0 0x1000>;
204 compatible = "virtio,mmio";
207 virtio_mmio@fe004000 {
208 interrupts = <0x14 0x4>;
209 interrupt-parent = <0x2>;
210 reg = <0x0 0xfe004000 0x0 0x1000>;
211 compatible = "virtio,mmio";
214 virtio_mmio@fe003000 {
215 interrupts = <0x13 0x4>;
216 interrupt-parent = <0x2>;
217 reg = <0x0 0xfe003000 0x0 0x1000>;
218 compatible = "virtio,mmio";
221 virtio_mmio@fe002000 {
222 interrupts = <0x12 0x4>;
223 interrupt-parent = <0x2>;
224 reg = <0x0 0xfe002000 0x0 0x1000>;
225 compatible = "virtio,mmio";
228 virtio_mmio@fe001000 {
229 interrupts = <0x11 0x4>;
230 interrupt-parent = <0x2>;
231 reg = <0x0 0xfe001000 0x0 0x1000>;
232 compatible = "virtio,mmio";
235 virtio_mmio@fe000000 {
236 interrupts = <0x10 0x4>;
237 interrupt-parent = <0x2>;
238 reg = <0x0 0xfe000000 0x0 0x1000>;
239 compatible = "virtio,mmio";
243 compatible = "cfi-flash";
244 reg = <0x0 0x88000000 0x0 0x1000>;
250 compatible = "andestech,atcspi200";
251 reg = <0x0 0xf0b00000 0x0 0x1000>;
252 #address-cells = <1>;
257 interrupt-parent = <&plic0>;
259 compatible = "jedec,spi-nor";
260 spi-max-frequency = <50000000>;