arch/riscv/dts/ae350_32.dts

   1 /dts-v1/;
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "andestech,a25";
   7         model = "andestech,a25";
   8
   9         aliases {
  10                 uart0 = &serial0;
  11                 spi0 = &spi;
  12         };
  13
  14         chosen {
  15                 bootargs = "console=ttyS0,38400n8  debug loglevel=7";
  16                 stdout-path = "uart0:38400n8";
  17         };
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22                 timebase-frequency = <60000000>;
  23                 CPU0: cpu@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         status = "okay";
  27                         compatible = "riscv";
  28                         riscv,isa = "rv32imafdc";
  29                         riscv,priv-major = <1>;
  30                         riscv,priv-minor = <10>;
  31                         mmu-type = "riscv,sv32";
  32                         clock-frequency = <60000000>;
  33                         i-cache-size = <0x8000>;
  34                         i-cache-line-size = <32>;
  35                         d-cache-size = <0x8000>;
  36                         d-cache-line-size = <32>;
  37                         next-level-cache = <&L2>;
  38                         CPU0_intc: interrupt-controller {
  39                                 #interrupt-cells = <1>;
  40                                 interrupt-controller;
  41                                 compatible = "riscv,cpu-intc";
  42                         };
  43                 };
  44                 CPU1: cpu@1 {
  45                         device_type = "cpu";
  46                         reg = <1>;
  47                         status = "okay";
  48                         compatible = "riscv";
  49                         riscv,isa = "rv32imafdc";
  50                         riscv,priv-major = <1>;
  51                         riscv,priv-minor = <10>;
  52                         mmu-type = "riscv,sv32";
  53                         clock-frequency = <60000000>;
  54                         i-cache-size = <0x8000>;
  55                         i-cache-line-size = <32>;
  56                         d-cache-size = <0x8000>;
  57                         d-cache-line-size = <32>;
  58                         next-level-cache = <&L2>;
  59                         CPU1_intc: interrupt-controller {
  60                                 #interrupt-cells = <1>;
  61                                 interrupt-controller;
  62                                 compatible = "riscv,cpu-intc";
  63                         };
  64                 };
  65         };
  66
  67         L2: l2-cache@e0500000 {
  68                 compatible = "v5l2cache";
  69                 cache-level = <2>;
  70                 cache-size = <0x40000>;
  71                 reg = <0xe0500000 0x40000>;
  72                 andes,inst-prefetch = <3>;
  73                 andes,data-prefetch = <3>;
  74                 /* The value format is <XRAMOCTL XRAMICTL> */
  75                 andes,tag-ram-ctl = <0 0>;
  76                 andes,data-ram-ctl = <0 0>;
  77         };
  78
  79         memory@0 {
  80                 device_type = "memory";
  81                 reg = <0x00000000 0x40000000>;
  82         };
  83
  84         soc {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 compatible = "simple-bus";
  88                 ranges;
  89
  90                 plic0: interrupt-controller@e4000000 {
  91                         compatible = "riscv,plic0";
  92                         #address-cells = <1>;
  93                         #interrupt-cells = <1>;
  94                         interrupt-controller;
  95                         reg = <0xe4000000 0x2000000>;
  96                         riscv,ndev=<71>;
  97                         interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
  98                 };
  99
 100                 plic1: interrupt-controller@e6400000 {
 101                         compatible = "riscv,plic1";
 102                         #address-cells = <1>;
 103                         #interrupt-cells = <1>;
 104                         interrupt-controller;
 105                         reg = <0xe6400000 0x400000>;
 106                         riscv,ndev=<2>;
 107                         interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
 108                 };
 109
 110                 plmt0@e6000000 {
 111                         compatible = "riscv,plmt0";
 112                         interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
 113                         reg = <0xe6000000 0x100000>;
 114                 };
 115         };
 116
 117         spiclk: virt_100mhz {
 118                 #clock-cells = <0>;
 119                 compatible = "fixed-clock";
 120                 clock-frequency = <100000000>;
 121         };
 122
 123         timer0: timer@f0400000 {
 124                 compatible = "andestech,atcpit100";
 125                 reg = <0xf0400000 0x1000>;
 126                 clock-frequency = <60000000>;
 127                 interrupts = <3 4>;
 128                 interrupt-parent = <&plic0>;
 129         };
 130
 131         serial0: serial@f0300000 {
 132                 compatible = "andestech,uart16550", "ns16550a";
 133                 reg = <0xf0300000 0x1000>;
 134                 interrupts = <9 4>;
 135                 clock-frequency = <19660800>;
 136                 reg-shift = <2>;
 137                 reg-offset = <32>;
 138                 no-loopback-test = <1>;
 139                 interrupt-parent = <&plic0>;
 140         };
 141
 142         mac0: mac@e0100000 {
 143                 compatible = "andestech,atmac100";
 144                 reg = <0xe0100000 0x1000>;
 145                 interrupts = <19 4>;
 146                 interrupt-parent = <&plic0>;
 147         };
 148
 149         mmc0: mmc@f0e00000 {
 150                 compatible = "andestech,atfsdc010";
 151                 max-frequency = <100000000>;
 152                 clock-freq-min-max = <400000 100000000>;
 153                 fifo-depth = <0x10>;
 154                 reg = <0xf0e00000 0x1000>;
 155                 interrupts = <18 4>;
 156                 cap-sd-highspeed;
 157                 interrupt-parent = <&plic0>;
 158         };
 159
 160         dma0: dma@f0c00000 {
 161                 compatible = "andestech,atcdmac300";
 162                 reg = <0xf0c00000 0x1000>;
 163                 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
 164                 dma-channels = <8>;
 165                 interrupt-parent = <&plic0>;
 166         };
 167
 168         lcd0: lcd@e0200000 {
 169                 compatible = "andestech,atflcdc100";
 170                 reg = <0xe0200000 0x1000>;
 171                 interrupts = <20 4>;
 172                 interrupt-parent = <&plic0>;
 173         };
 174
 175         smc0: smc@e0400000 {
 176                 compatible = "andestech,atfsmc020";
 177                 reg = <0xe0400000 0x1000>;
 178         };
 179
 180         snd0: snd@f0d00000 {
 181                 compatible = "andestech,atfac97";
 182                 reg = <0xf0d00000 0x1000>;
 183                 interrupts = <17 4>;
 184                 interrupt-parent = <&plic0>;
 185         };
 186
 187         pmu {
 188                 compatible = "riscv,base-pmu";
 189         };
 190
 191         virtio_mmio@fe007000 {
 192                 interrupts = <0x17 0x4>;
 193                 interrupt-parent = <0x2>;
 194                 reg = <0xfe007000 0x1000>;
 195                 compatible = "virtio,mmio";
 196         };
 197
 198         virtio_mmio@fe006000 {
 199                 interrupts = <0x16 0x4>;
 200                 interrupt-parent = <0x2>;
 201                 reg = <0xfe006000 0x1000>;
 202                 compatible = "virtio,mmio";
 203         };
 204
 205         virtio_mmio@fe005000 {
 206                 interrupts = <0x15 0x4>;
 207                 interrupt-parent = <0x2>;
 208                 reg = <0xfe005000 0x1000>;
 209                 compatible = "virtio,mmio";
 210         };
 211
 212         virtio_mmio@fe004000 {
 213                 interrupts = <0x14 0x4>;
 214                 interrupt-parent = <0x2>;
 215                 reg = <0xfe004000 0x1000>;
 216                 compatible = "virtio,mmio";
 217         };
 218
 219         virtio_mmio@fe003000 {
 220                 interrupts = <0x13 0x4>;
 221                 interrupt-parent = <0x2>;
 222                 reg = <0xfe003000 0x1000>;
 223                 compatible = "virtio,mmio";
 224         };
 225
 226         virtio_mmio@fe002000 {
 227                 interrupts = <0x12 0x4>;
 228                 interrupt-parent = <0x2>;
 229                 reg = <0xfe002000 0x1000>;
 230                 compatible = "virtio,mmio";
 231         };
 232
 233         virtio_mmio@fe001000 {
 234                 interrupts = <0x11 0x4>;
 235                 interrupt-parent = <0x2>;
 236                 reg = <0xfe001000 0x1000>;
 237                 compatible = "virtio,mmio";
 238         };
 239
 240         virtio_mmio@fe000000 {
 241                 interrupts = <0x10 0x4>;
 242                 interrupt-parent = <0x2>;
 243                 reg = <0xfe000000 0x1000>;
 244                 compatible = "virtio,mmio";
 245         };
 246
 247         nor@0,0 {
 248                 compatible = "cfi-flash";
 249                 reg = <0x88000000 0x1000>;
 250                 bank-width = <2>;
 251                 device-width = <1>;
 252         };
 253
 254         spi: spi@f0b00000 {
 255                 compatible = "andestech,atcspi200";
 256                 reg = <0xf0b00000 0x1000>;
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 num-cs = <1>;
 260                 clocks = <&spiclk>;
 261                 interrupts = <4 4>;
 262                 interrupt-parent = <&plic0>;
 263                 flash@0 {
 264                         compatible = "jedec,spi-nor";
 265                         spi-max-frequency = <50000000>;
 266                         reg = <0>;
 267                         spi-cpol;
 268                         spi-cpha;
 269                 };
 270         };
 271 };