arch/riscv/dts/ae250.dts

   1 /dts-v1/;
   2 / {
   3         compatible = "riscv32 nx25";
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         interrupt-parent = <&intc>;
   7
   8         aliases {
   9                 uart0 = &serial0;
  10                 ethernet0 = &mac0;
  11                 spi0 = &spi;
  12         } ;
  13
  14         chosen {
  15                 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
  16                 stdout-path = "uart0:38400n8";
  17                 tick-timer = &timer0;
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x00000000 0x40000000>;
  23         };
  24
  25         spiclk: virt_100mhz {
  26                 #clock-cells = <0>;
  27                 compatible = "fixed-clock";
  28                 clock-frequency = <100000000>;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34                 cpu@0 {
  35                         compatible = "andestech,n13";
  36                         reg = <0>;
  37                         /* FIXME: to fill correct frqeuency */
  38                         clock-frequency = <60000000>;
  39                 };
  40         };
  41
  42         intc: interrupt-controller {
  43                 compatible = "andestech,atnointc010";
  44                 #interrupt-cells = <1>;
  45                 interrupt-controller;
  46         };
  47
  48         serial0: serial@f0300000 {
  49                 compatible = "andestech,uart16550", "ns16550a";
  50                 reg = <0xf0300000 0x1000>;
  51                 interrupts = <7 4>;
  52                 clock-frequency = <19660800>;
  53                 reg-shift = <2>;
  54                 reg-offset = <32>;
  55                 no-loopback-test = <1>;
  56         };
  57
  58         timer0: timer@f0400000 {
  59                 compatible = "andestech,atcpit100";
  60                 reg = <0xf0400000 0x1000>;
  61                 interrupts = <2 4>;
  62                 clock-frequency = <40000000>;
  63         };
  64
  65         mac0: mac@e0100000 {
  66                 compatible = "andestech,atmac100";
  67                 reg = <0xe0100000 0x1000>;
  68                 interrupts = <25 4>;
  69         };
  70
  71         mmc0: mmc@f0e00000 {
  72                 compatible = "andestech,atsdc010";
  73                 max-frequency = <100000000>;
  74                 fifo-depth = <0x10>;
  75                 reg = <0xf0e00000 0x1000>;
  76                 interrupts = <17 4>;
  77                 cap-sd-highspeed;
  78         };
  79
  80         spi: spi@f0b00000 {
  81                 compatible = "andestech,atcspi200";
  82                 reg = <0xf0b00000 0x1000>;
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 num-cs = <1>;
  86                 clocks = <&spiclk>;
  87                 interrupts = <3 4>;
  88                         flash@0 {
  89                         compatible = "spi-flash";
  90                         spi-max-frequency = <50000000>;
  91                         reg = <0>;
  92                         spi-cpol;
  93                         spi-cpha;
  94                 };
  95         };
  96
  97 };