1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
16 #include <asm/encoding.h>
17 #include <generated/asm-offsets.h>
23 #define RELOC_TYPE R_RISCV_32
30 #define RELOC_TYPE R_RISCV_64
31 #define SYM_INDEX 0x20
36 secondary_harts_relocation_error:
37 .ascii "Relocation of secondary harts has failed, error %d\n"
42 #ifdef CONFIG_RISCV_MMODE
46 /* save hart id and dtb pointer */
51 csrw MODE_PREFIX(tvec), t0
53 /* mask all interrupts */
54 csrw MODE_PREFIX(ie), zero
57 /* check if hart is within range */
60 bge tp, t0, hart_out_of_bounds_loop
64 /* set xSIE bit to receive IPIs */
65 #ifdef CONFIG_RISCV_MMODE
70 csrs MODE_PREFIX(ie), t0
74 * Set stackpointer in internal/ex RAM to call board_init_f
78 li t1, CONFIG_SYS_INIT_SP_ADDR
79 and sp, t1, t0 /* force 16 byte alignment */
83 jal board_init_f_alloc_reserve
86 * Set global data pointer here for all harts, uninitialized at this
94 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
102 * Pick hart to initialize global data and run U-Boot. The other harts
103 * wait for initialization to complete.
107 amoswap.w s2, t1, 0(t0)
108 bnez s2, wait_for_gd_init
110 bnez tp, secondary_hart_loop
113 #ifdef CONFIG_OF_PRIOR_STAGE
114 la t0, prior_stage_fdt_address
118 jal board_init_f_init_reserve
120 /* save the boot hart id to global_data */
121 SREG tp, GD_BOOT_HART(gp)
124 la t0, available_harts_lock
126 amoswap.w zero, zero, 0(t0)
129 la t0, available_harts_lock
131 1: amoswap.w t1, t1, 0(t0)
135 /* register available harts in the available_harts mask */
138 LREG t2, GD_AVAILABLE_HARTS(gp)
140 SREG t2, GD_AVAILABLE_HARTS(gp)
143 amoswap.w zero, zero, 0(t0)
146 * Continue on hart lottery winner, others branch to
147 * secondary_hart_loop.
149 bnez s2, secondary_hart_loop
156 #ifdef CONFIG_DEBUG_UART
160 mv a0, zero /* a0 <-- boot_flags = 0 */
162 jr t5 /* jump to board_init_f() */
165 * void relocate_code (addr_sp, gd, addr_moni)
167 * This "function" does not return, instead it continues in RAM
168 * after relocating the monitor code.
173 mv s2, a0 /* save addr_sp */
174 mv s3, a1 /* save addr of gd */
175 mv s4, a2 /* save addr of destination */
183 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
190 sub t6, s4, t0 /* t6 <- relocation offset */
191 beq t0, s4, clear_bss /* skip relocation */
193 mv t1, s4 /* t1 <- scratch for copy_loop */
195 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
196 add t2, t0, t3 /* t2 <- source end address */
200 addi t0, t0, REGBYTES
202 addi t1, t1, REGBYTES
203 blt t0, t2, copy_loop
206 * Update dynamic relocations after board_init_f
209 la t1, __rel_dyn_start
211 beq t1, t2, clear_bss
212 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
213 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
216 * skip first reserved entry: address, type, addend
221 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
222 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
223 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
224 LREG t3, -(REGBYTES*3)(t1)
225 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
226 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
227 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
230 addi t1, t1, (REGBYTES*3)
234 la t4, __dyn_sym_start
238 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
239 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
240 andi t5, t5, 0xFF /* t5 <--- relocation type */
242 bne t5, t3, 10f /* skip non-addned entries */
244 LREG t3, -(REGBYTES*3)(t1)
248 LREG t5, REGBYTES(s5)
249 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
250 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
253 addi t1, t1, (REGBYTES*3)
261 csrw MODE_PREFIX(tvec), t0
264 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
265 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
266 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
267 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
268 beq t0, t1, relocate_secondary_harts
271 SREG zero, 0(t0) /* clear loop... */
272 addi t0, t0, REGBYTES
275 relocate_secondary_harts:
277 /* send relocation IPI */
278 la t0, secondary_hart_relocate
281 /* store relocation offset */
286 jal smp_call_function
288 /* hang if relocation of secondary harts has failed */
291 la a0, secondary_harts_relocation_error
295 /* restore relocation offset */
300 * We are done. Do not return, instead branch to second part of board
301 * initialization, now running from RAM.
304 jal invalidate_icache_all
307 mv t4, t0 /* offset of board_init_r() */
308 add t4, t4, t6 /* real address of board_init_r() */
310 * setup parameters for board_init_r
313 mv a1, s4 /* dest_addr */
318 jr t4 /* jump to board_init_r() */
321 hart_out_of_bounds_loop:
322 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
324 j hart_out_of_bounds_loop
328 /* SMP relocation entry */
329 secondary_hart_relocate:
335 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
338 /* update global data pointer */
346 csrr t0, MODE_PREFIX(ip)
347 #ifdef CONFIG_RISCV_MMODE
348 andi t0, t0, MIE_MSIE
350 andi t0, t0, SIE_SSIE
352 beqz t0, secondary_hart_loop
358 j secondary_hart_loop