1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
16 #include <asm/encoding.h>
17 #include <generated/asm-offsets.h>
23 #define RELOC_TYPE R_RISCV_32
30 #define RELOC_TYPE R_RISCV_64
31 #define SYM_INDEX 0x20
36 secondary_harts_relocation_error:
37 .ascii "Relocation of secondary harts has failed, error %d\n"
42 #if CONFIG_IS_ENABLED(RISCV_MMODE)
46 /* save hart id and dtb pointer */
51 csrw MODE_PREFIX(tvec), t0
53 /* mask all interrupts */
54 csrw MODE_PREFIX(ie), zero
57 /* check if hart is within range */
60 bge tp, t0, hart_out_of_bounds_loop
64 /* set xSIE bit to receive IPIs */
65 #if CONFIG_IS_ENABLED(RISCV_MMODE)
70 csrs MODE_PREFIX(ie), t0
74 * Set stackpointer in internal/ex RAM to call board_init_f
78 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
79 li t1, CONFIG_SPL_STACK
81 li t1, CONFIG_SYS_INIT_SP_ADDR
83 and sp, t1, t0 /* force 16 byte alignment */
87 jal board_init_f_alloc_reserve
90 * Set global data pointer here for all harts, uninitialized at this
98 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
106 * Pick hart to initialize global data and run U-Boot. The other harts
107 * wait for initialization to complete.
111 amoswap.w s2, t1, 0(t0)
112 bnez s2, wait_for_gd_init
114 bnez tp, secondary_hart_loop
117 #ifdef CONFIG_OF_PRIOR_STAGE
118 la t0, prior_stage_fdt_address
122 jal board_init_f_init_reserve
124 /* save the boot hart id to global_data */
125 SREG tp, GD_BOOT_HART(gp)
128 la t0, available_harts_lock
130 amoswap.w zero, zero, 0(t0)
133 la t0, available_harts_lock
135 1: amoswap.w t1, t1, 0(t0)
139 /* register available harts in the available_harts mask */
142 LREG t2, GD_AVAILABLE_HARTS(gp)
144 SREG t2, GD_AVAILABLE_HARTS(gp)
147 amoswap.w zero, zero, 0(t0)
150 * Continue on hart lottery winner, others branch to
151 * secondary_hart_loop.
153 bnez s2, secondary_hart_loop
160 #ifdef CONFIG_DEBUG_UART
164 mv a0, zero /* a0 <-- boot_flags = 0 */
166 jalr t5 /* jump to board_init_f() */
168 #ifdef CONFIG_SPL_BUILD
172 beq t0, t1, spl_stack_gd_setup
176 addi t0, t0, REGBYTES
177 bne t0, t1, spl_clear_bss_loop
180 jal spl_relocate_stack_gd
182 /* skip setup if we did not relocate */
183 beqz a0, spl_call_board_init_r
186 /* setup stack on main hart */
189 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
195 /* set new stack and global data pointer on secondary harts */
196 spl_secondary_hart_stack_gd_setup:
197 la a0, secondary_hart_relocate
200 jal smp_call_function
202 /* hang if relocation of secondary harts has failed */
205 la a0, secondary_harts_relocation_error
209 /* set new global data pointer on main hart */
212 spl_call_board_init_r:
219 * void relocate_code (addr_sp, gd, addr_moni)
221 * This "function" does not return, instead it continues in RAM
222 * after relocating the monitor code.
227 mv s2, a0 /* save addr_sp */
228 mv s3, a1 /* save addr of gd */
229 mv s4, a2 /* save addr of destination */
237 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
244 sub t6, s4, t0 /* t6 <- relocation offset */
245 beq t0, s4, clear_bss /* skip relocation */
247 mv t1, s4 /* t1 <- scratch for copy_loop */
249 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
250 add t2, t0, t3 /* t2 <- source end address */
254 addi t0, t0, REGBYTES
256 addi t1, t1, REGBYTES
257 blt t0, t2, copy_loop
260 * Update dynamic relocations after board_init_f
263 la t1, __rel_dyn_start
265 beq t1, t2, clear_bss
266 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
267 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
270 * skip first reserved entry: address, type, addend
275 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
276 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
277 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
278 LREG t3, -(REGBYTES*3)(t1)
279 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
280 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
281 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
284 addi t1, t1, (REGBYTES*3)
288 la t4, __dyn_sym_start
292 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
293 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
294 andi t5, t5, 0xFF /* t5 <--- relocation type */
296 bne t5, t3, 10f /* skip non-addned entries */
298 LREG t3, -(REGBYTES*3)(t1)
302 LREG t5, REGBYTES(s5)
303 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
304 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
307 addi t1, t1, (REGBYTES*3)
315 csrw MODE_PREFIX(tvec), t0
318 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
319 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
320 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
321 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
322 beq t0, t1, relocate_secondary_harts
325 SREG zero, 0(t0) /* clear loop... */
326 addi t0, t0, REGBYTES
329 relocate_secondary_harts:
331 /* send relocation IPI */
332 la t0, secondary_hart_relocate
335 /* store relocation offset */
340 jal smp_call_function
342 /* hang if relocation of secondary harts has failed */
345 la a0, secondary_harts_relocation_error
349 /* restore relocation offset */
354 * We are done. Do not return, instead branch to second part of board
355 * initialization, now running from RAM.
358 jal invalidate_icache_all
361 mv t4, t0 /* offset of board_init_r() */
362 add t4, t4, t6 /* real address of board_init_r() */
364 * setup parameters for board_init_r
367 mv a1, s4 /* dest_addr */
372 jr t4 /* jump to board_init_r() */
375 hart_out_of_bounds_loop:
376 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
378 j hart_out_of_bounds_loop
382 /* SMP relocation entry */
383 secondary_hart_relocate:
389 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
392 /* update global data pointer */
400 csrr t0, MODE_PREFIX(ip)
401 #if CONFIG_IS_ENABLED(RISCV_MMODE)
402 andi t0, t0, MIE_MSIE
404 andi t0, t0, SIE_SSIE
406 beqz t0, secondary_hart_loop
412 j secondary_hart_loop