1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_FU540
21 bool "Support SiFive FU540 Board"
26 bool "Do not enable icache"
29 Do not enable instruction cache in U-Boot.
31 config SPL_SYS_ICACHE_OFF
32 bool "Do not enable icache in SPL"
34 default SYS_ICACHE_OFF
36 Do not enable instruction cache in SPL.
39 bool "Do not enable dcache"
42 Do not enable data cache in U-Boot.
44 config SPL_SYS_DCACHE_OFF
45 bool "Do not enable dcache in SPL"
47 default SYS_DCACHE_OFF
49 Do not enable data cache in SPL.
51 # board-specific options below
52 source "board/AndesTech/ax25-ae350/Kconfig"
53 source "board/emulation/qemu-riscv/Kconfig"
54 source "board/microchip/mpfs_icicle/Kconfig"
55 source "board/sifive/fu540/Kconfig"
57 # platform-specific options below
58 source "arch/riscv/cpu/ax25/Kconfig"
59 source "arch/riscv/cpu/fu540/Kconfig"
60 source "arch/riscv/cpu/generic/Kconfig"
62 # architecture-specific options below
72 Choose this option to target the RV32I base integer instruction set.
79 Choose this option to target the RV64I base integer instruction set.
88 bool "medium low code model"
90 U-Boot and its statically defined symbols must lie within a single 2 GiB
91 address range and must lie between absolute addresses -2 GiB and +2 GiB.
94 bool "medium any code model"
96 U-Boot and its statically defined symbols must be within any single 2 GiB
108 Choose this option to build U-Boot for RISC-V M-Mode.
113 Choose this option to build U-Boot for RISC-V S-Mode.
118 prompt "SPL Run Mode"
119 default SPL_RISCV_MMODE
122 config SPL_RISCV_MMODE
125 Choose this option to build U-Boot SPL for RISC-V M-Mode.
127 config SPL_RISCV_SMODE
130 Choose this option to build U-Boot SPL for RISC-V S-Mode.
135 bool "Emit compressed instructions"
138 Adds "C" to the ISA subsets that the toolchain is allowed to emit
139 when building U-Boot, which results in compressed instructions in the
153 depends on RISCV_MMODE || SPL_RISCV_MMODE
156 select SPL_REGMAP if SPL
157 select SPL_SYSCON if SPL
159 The SiFive CLINT block holds memory-mapped control and status registers
160 associated with software and timer interrupts.
164 depends on RISCV_MMODE || SPL_RISCV_MMODE
167 select SPL_REGMAP if SPL
168 select SPL_SYSCON if SPL
170 The Andes PLIC block holds memory-mapped claim and pending registers
171 associated with software interrupt.
175 depends on RISCV_MMODE || SPL_RISCV_MMODE
178 select SPL_REGMAP if SPL
179 select SPL_SYSCON if SPL
181 The Andes PLMT block holds memory-mapped mtime register
182 associated with timer tick.
186 default y if RISCV_SMODE || SPL_RISCV_SMODE
188 The provides the riscv_get_time() API that is implemented using the
189 standard rdtime instruction. This is the case for S-mode U-Boot, and
190 is useful for processors that support rdtime in M-mode too.
192 config SYS_MALLOC_F_LEN
196 bool "Symmetric Multi-Processing"
197 depends on SBI_V01 || !RISCV_SMODE
199 This enables support for systems with more than one CPU. If
200 you say N here, U-Boot will run on single and multiprocessor
201 machines, but will use only one CPU of a multiprocessor
202 machine. If you say Y here, U-Boot will run on many, but not
203 all, single processor machines.
206 bool "Symmetric Multi-Processing in SPL"
207 depends on SPL && SPL_RISCV_MMODE
210 This enables support for systems with more than one CPU in SPL.
211 If you say N here, U-Boot SPL will run on single and multiprocessor
212 machines, but will use only one CPU of a multiprocessor
213 machine. If you say Y here, U-Boot SPL will run on many, but not
214 all, single processor machines.
217 int "Maximum number of CPUs (2-32)"
219 depends on SMP || SPL_SMP
222 On multiprocessor machines, U-Boot sets up a stack for each CPU.
223 Stack memory is pre-allocated. U-Boot must therefore know the
224 maximum number of CPUs that may be present.
228 default y if RISCV_SMODE || SPL_RISCV_SMODE
235 bool "SBI v0.1 support"
238 This config allows kernel to use SBI v0.1 APIs. This will be
239 deprecated in future once legacy M-mode software are no longer in use.
242 bool "SBI v0.2 support"
245 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
246 scalable and extendable to handle future needs for RISC-V supervisor
247 interfaces. For example, with SBI v0.2 HSM extension, only a single
248 hart need to boot and enter operating system. The booting hart can
249 bring up secondary harts one by one afterwards.
251 Choose this option if OpenSBI v0.7 or above release is used together
259 default y if RISCV_SMODE || SPL_RISCV_SMODE
265 XIP (eXecute In Place) is a method for executing code directly
266 from a NOR flash memory without copying the code to ram.
267 Say yes here if U-Boot boots from flash directly.
270 bool "Show registers on unhandled exception"
272 config STACK_SIZE_SHIFT