1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_FU540
21 bool "Support SiFive FU540 Board"
26 bool "Do not enable icache"
29 Do not enable instruction cache in U-Boot.
31 config SPL_SYS_ICACHE_OFF
32 bool "Do not enable icache in SPL"
34 default SYS_ICACHE_OFF
36 Do not enable instruction cache in SPL.
39 bool "Do not enable dcache"
42 Do not enable data cache in U-Boot.
44 config SPL_SYS_DCACHE_OFF
45 bool "Do not enable dcache in SPL"
47 default SYS_DCACHE_OFF
49 Do not enable data cache in SPL.
51 # board-specific options below
52 source "board/AndesTech/ax25-ae350/Kconfig"
53 source "board/emulation/qemu-riscv/Kconfig"
54 source "board/microchip/mpfs_icicle/Kconfig"
55 source "board/sifive/fu540/Kconfig"
57 # platform-specific options below
58 source "arch/riscv/cpu/ax25/Kconfig"
59 source "arch/riscv/cpu/generic/Kconfig"
61 # architecture-specific options below
71 Choose this option to target the RV32I base integer instruction set.
78 Choose this option to target the RV64I base integer instruction set.
87 bool "medium low code model"
89 U-Boot and its statically defined symbols must lie within a single 2 GiB
90 address range and must lie between absolute addresses -2 GiB and +2 GiB.
93 bool "medium any code model"
95 U-Boot and its statically defined symbols must be within any single 2 GiB
107 Choose this option to build U-Boot for RISC-V M-Mode.
112 Choose this option to build U-Boot for RISC-V S-Mode.
117 prompt "SPL Run Mode"
118 default SPL_RISCV_MMODE
121 config SPL_RISCV_MMODE
124 Choose this option to build U-Boot SPL for RISC-V M-Mode.
126 config SPL_RISCV_SMODE
129 Choose this option to build U-Boot SPL for RISC-V S-Mode.
134 bool "Emit compressed instructions"
137 Adds "C" to the ISA subsets that the toolchain is allowed to emit
138 when building U-Boot, which results in compressed instructions in the
152 depends on RISCV_MMODE || SPL_RISCV_MMODE
155 select SPL_REGMAP if SPL
156 select SPL_SYSCON if SPL
158 The SiFive CLINT block holds memory-mapped control and status registers
159 associated with software and timer interrupts.
163 depends on RISCV_MMODE || SPL_RISCV_MMODE
166 select SPL_REGMAP if SPL
167 select SPL_SYSCON if SPL
169 The Andes PLIC block holds memory-mapped claim and pending registers
170 associated with software interrupt.
174 depends on RISCV_MMODE || SPL_RISCV_MMODE
177 select SPL_REGMAP if SPL
178 select SPL_SYSCON if SPL
180 The Andes PLMT block holds memory-mapped mtime register
181 associated with timer tick.
185 default y if RISCV_SMODE || SPL_RISCV_SMODE
187 The provides the riscv_get_time() API that is implemented using the
188 standard rdtime instruction. This is the case for S-mode U-Boot, and
189 is useful for processors that support rdtime in M-mode too.
191 config SYS_MALLOC_F_LEN
195 bool "Symmetric Multi-Processing"
197 This enables support for systems with more than one CPU. If
198 you say N here, U-Boot will run on single and multiprocessor
199 machines, but will use only one CPU of a multiprocessor
200 machine. If you say Y here, U-Boot will run on many, but not
201 all, single processor machines.
204 int "Maximum number of CPUs (2-32)"
209 On multiprocessor machines, U-Boot sets up a stack for each CPU.
210 Stack memory is pre-allocated. U-Boot must therefore know the
211 maximum number of CPUs that may be present.
215 default y if RISCV_SMODE || SPL_RISCV_SMODE
221 XIP (eXecute In Place) is a method for executing code directly
222 from a NOR flash memory without copying the code to ram.
223 Say yes here if U-Boot boots from flash directly.
225 config STACK_SIZE_SHIFT
230 default "arch/riscv/cpu/u-boot-spl.lds"