2 * Support for SCC external PCI
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 #include <linux/kernel.h>
24 #include <linux/threads.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/pci_regs.h>
28 #include <linux/bootmem.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/ppc-pci.h>
36 #include "celleb_scc.h"
37 #include "celleb_pci.h"
39 #define MAX_PCI_DEVICES 32
40 #define MAX_PCI_FUNCTIONS 8
42 #define iob() __asm__ __volatile__("eieio; sync":::"memory")
44 static inline PCI_IO_ADDR celleb_epci_get_epci_base(
45 struct pci_controller *hose)
49 * Celleb epci uses cfg_addr as a base address for
50 * epci control registers.
53 return hose->cfg_addr;
56 static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
57 struct pci_controller *hose)
61 * Celleb epci uses cfg_data as a base address for
62 * configuration area for epci devices.
65 return hose->cfg_data;
68 static inline void clear_and_disable_master_abort_interrupt(
69 struct pci_controller *hose)
71 PCI_IO_ADDR epci_base;
73 epci_base = celleb_epci_get_epci_base(hose);
74 reg = epci_base + PCI_COMMAND;
75 out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
78 static int celleb_epci_check_abort(struct pci_controller *hose,
82 PCI_IO_ADDR epci_base;
86 epci_base = celleb_epci_get_epci_base(hose);
88 reg = epci_base + PCI_COMMAND;
91 if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
93 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
95 /* clear PCI Controller error, FRE, PMFE */
96 reg = epci_base + SCC_EPCI_STATUS;
97 out_be32(reg, SCC_EPCI_INT_PAI);
99 reg = epci_base + SCC_EPCI_VCSR;
100 val = in_be32(reg) & 0xffff;
101 val |= SCC_EPCI_VCSR_FRE;
104 reg = epci_base + SCC_EPCI_VISTAT;
105 out_be32(reg, SCC_EPCI_VISTAT_PMFE);
106 return PCIBIOS_DEVICE_NOT_FOUND;
109 return PCIBIOS_SUCCESSFUL;
112 static PCI_IO_ADDR celleb_epci_make_config_addr(struct pci_bus *bus,
113 struct pci_controller *hose, unsigned int devfn, int where)
117 if (bus != hose->bus)
118 addr = celleb_epci_get_epci_cfg(hose) +
119 (((bus->number & 0xff) << 16)
120 | ((devfn & 0xff) << 8)
124 addr = celleb_epci_get_epci_cfg(hose) +
125 (((devfn & 0xff) << 8) | (where & 0xff));
127 pr_debug("EPCI: config_addr = 0x%p\n", addr);
132 static int celleb_epci_read_config(struct pci_bus *bus,
133 unsigned int devfn, int where, int size, u32 *val)
135 PCI_IO_ADDR epci_base;
137 struct pci_controller *hose = pci_bus_to_host(bus);
139 /* allignment check */
140 BUG_ON(where % size);
142 if (!celleb_epci_get_epci_cfg(hose))
143 return PCIBIOS_DEVICE_NOT_FOUND;
145 if (bus->number == hose->first_busno && devfn == 0) {
146 /* EPCI controller self */
148 epci_base = celleb_epci_get_epci_base(hose);
149 addr = epci_base + where;
156 *val = in_be16(addr);
159 *val = in_be32(addr);
162 return PCIBIOS_DEVICE_NOT_FOUND;
167 clear_and_disable_master_abort_interrupt(hose);
168 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
175 *val = in_le16(addr);
178 *val = in_le32(addr);
181 return PCIBIOS_DEVICE_NOT_FOUND;
186 "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
187 addr, devfn, where, size, *val);
189 return celleb_epci_check_abort(hose, NULL);
192 static int celleb_epci_write_config(struct pci_bus *bus,
193 unsigned int devfn, int where, int size, u32 val)
195 PCI_IO_ADDR epci_base;
197 struct pci_controller *hose = pci_bus_to_host(bus);
199 /* allignment check */
200 BUG_ON(where % size);
202 if (!celleb_epci_get_epci_cfg(hose))
203 return PCIBIOS_DEVICE_NOT_FOUND;
205 if (bus->number == hose->first_busno && devfn == 0) {
206 /* EPCI controller self */
208 epci_base = celleb_epci_get_epci_base(hose);
209 addr = epci_base + where;
222 return PCIBIOS_DEVICE_NOT_FOUND;
227 clear_and_disable_master_abort_interrupt(hose);
228 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
241 return PCIBIOS_DEVICE_NOT_FOUND;
245 return celleb_epci_check_abort(hose, addr);
248 struct pci_ops celleb_epci_ops = {
249 .read = celleb_epci_read_config,
250 .write = celleb_epci_write_config,
253 /* to be moved in FW */
254 static int __init celleb_epci_init(struct pci_controller *hose)
258 PCI_IO_ADDR epci_base;
261 epci_base = celleb_epci_get_epci_base(hose);
263 /* PCI core reset(Internal bus and PCI clock) */
264 reg = epci_base + SCC_EPCI_CKCTRL;
266 if (val == 0x00030101)
269 val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
272 /* set PCI core clock */
274 val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
277 /* release PCI core reset (internal bus) */
279 val |= SCC_EPCI_CKCTRL_CRST0;
282 /* set PCI clock select */
283 reg = epci_base + SCC_EPCI_CLKRST;
285 val &= ~SCC_EPCI_CLKRST_CKS_MASK;
286 val |= SCC_EPCI_CLKRST_CKS_2;
290 reg = epci_base + SCC_EPCI_ABTSET;
291 out_be32(reg, 0x0f1f001f); /* temporary value */
294 reg = epci_base + SCC_EPCI_CLKRST;
296 val |= SCC_EPCI_CLKRST_BC;
299 /* PCI clock enable */
301 val |= SCC_EPCI_CLKRST_PCKEN;
304 /* release PCI core reset (all) */
305 reg = epci_base + SCC_EPCI_CKCTRL;
307 val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
310 /* set base translation registers. (already set by Beat) */
312 /* set base address masks. (already set by Beat) */
315 /* release interrupt masks and clear all interrupts */
316 reg = epci_base + SCC_EPCI_INTSET;
317 out_be32(reg, 0x013f011f); /* all interrupts enable */
318 reg = epci_base + SCC_EPCI_VIENAB;
319 val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
321 reg = epci_base + SCC_EPCI_STATUS;
322 out_be32(reg, 0xffffffff);
323 reg = epci_base + SCC_EPCI_VISTAT;
324 out_be32(reg, 0xffffffff);
326 /* disable PCI->IB address translation */
327 reg = epci_base + SCC_EPCI_VCSR;
329 val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
332 /* set base addresses. (no need to set?) */
334 /* memory space, bus master enable */
335 reg = epci_base + PCI_COMMAND;
336 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
339 /* endian mode setup */
340 reg = epci_base + SCC_EPCI_ECMODE;
344 /* set control option */
345 reg = epci_base + SCC_EPCI_CNTOPT;
347 val |= SCC_EPCI_CNTOPT_O2PMB;
350 /* XXX: temporay: set registers for address conversion setup */
351 reg = epci_base + SCC_EPCI_CNF10_REG;
352 out_be32(reg, 0x80000008);
353 reg = epci_base + SCC_EPCI_CNF14_REG;
354 out_be32(reg, 0x40000008);
356 reg = epci_base + SCC_EPCI_BAM0;
357 out_be32(reg, 0x80000000);
358 reg = epci_base + SCC_EPCI_BAM1;
359 out_be32(reg, 0xe0000000);
361 reg = epci_base + SCC_EPCI_PVBAT;
362 out_be32(reg, 0x80000000);
365 /* release external PCI reset */
366 reg = epci_base + SCC_EPCI_CLKRST;
368 val |= SCC_EPCI_CLKRST_PCIRST;
375 static int __init celleb_setup_epci(struct device_node *node,
376 struct pci_controller *hose)
380 pr_debug("PCI: celleb_setup_epci()\n");
384 * Celleb epci uses cfg_addr and cfg_data member of
385 * pci_controller structure in irregular way.
387 * cfg_addr is used to map for control registers of
390 * cfg_data is used for configuration area of devices
391 * on Celleb epci buses.
394 if (of_address_to_resource(node, 0, &r))
396 hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
399 pr_debug("EPCI: cfg_addr map 0x%016llx->0x%016lx + 0x%016llx\n",
400 r.start, (unsigned long)hose->cfg_addr, (r.end - r.start + 1));
402 if (of_address_to_resource(node, 2, &r))
404 hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
407 pr_debug("EPCI: cfg_data map 0x%016llx->0x%016lx + 0x%016llx\n",
408 r.start, (unsigned long)hose->cfg_data, (r.end - r.start + 1));
410 hose->ops = &celleb_epci_ops;
411 celleb_epci_init(hose);
417 iounmap(hose->cfg_addr);
420 iounmap(hose->cfg_data);
424 struct celleb_phb_spec celleb_epci_spec __initdata = {
425 .setup = celleb_setup_epci,
426 .ops = &spiderpci_ops,
427 .iowa_init = &spiderpci_iowa_init,
428 .iowa_data = (void *)0,