1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
14 * PowerPC Hashed Page Table functions
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
37 #include <linux/cpu.h>
39 #include <asm/debugfs.h>
40 #include <asm/processor.h>
41 #include <asm/pgtable.h>
43 #include <asm/mmu_context.h>
45 #include <asm/types.h>
46 #include <linux/uaccess.h>
47 #include <asm/machdep.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
63 #include <asm/pte-walk.h>
64 #include <asm/asm-prototypes.h>
66 #include <mm/mmu_decl.h>
69 #define DBG(fmt...) udbg_printf(fmt)
75 #define DBG_LOW(fmt...) udbg_printf(fmt)
77 #define DBG_LOW(fmt...)
85 * Note: pte --> Linux PTE
86 * HPTE --> PowerPC Hashed Page Table Entry
89 * htab_initialize is called with the MMU off (of course), but
90 * the kernel has been copied down to zero so it can directly
91 * reference global data. At this point it is very difficult
92 * to print debug info.
96 static unsigned long _SDR1;
97 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
98 EXPORT_SYMBOL_GPL(mmu_psize_defs);
100 u8 hpte_page_sizes[1 << LP_BITS];
101 EXPORT_SYMBOL_GPL(hpte_page_sizes);
103 struct hash_pte *htab_address;
104 unsigned long htab_size_bytes;
105 unsigned long htab_hash_mask;
106 EXPORT_SYMBOL_GPL(htab_hash_mask);
107 int mmu_linear_psize = MMU_PAGE_4K;
108 EXPORT_SYMBOL_GPL(mmu_linear_psize);
109 int mmu_virtual_psize = MMU_PAGE_4K;
110 int mmu_vmalloc_psize = MMU_PAGE_4K;
111 #ifdef CONFIG_SPARSEMEM_VMEMMAP
112 int mmu_vmemmap_psize = MMU_PAGE_4K;
114 int mmu_io_psize = MMU_PAGE_4K;
115 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
116 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
117 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
118 u16 mmu_slb_size = 64;
119 EXPORT_SYMBOL_GPL(mmu_slb_size);
120 #ifdef CONFIG_PPC_64K_PAGES
121 int mmu_ci_restrictions;
123 #ifdef CONFIG_DEBUG_PAGEALLOC
124 static u8 *linear_map_hash_slots;
125 static unsigned long linear_map_hash_count;
126 static DEFINE_SPINLOCK(linear_map_hash_lock);
127 #endif /* CONFIG_DEBUG_PAGEALLOC */
128 struct mmu_hash_ops mmu_hash_ops;
129 EXPORT_SYMBOL(mmu_hash_ops);
132 * These are definitions of page sizes arrays to be used when none
133 * is provided by the firmware.
137 * Fallback (4k pages only)
139 static struct mmu_psize_def mmu_psize_defaults[] = {
143 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
150 * POWER4, GPUL, POWER5
152 * Support for 16Mb large pages
154 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
158 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
165 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
166 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
173 * 'R' and 'C' update notes:
174 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
175 * create writeable HPTEs without C set, because the hcall H_PROTECT
176 * that we use in that case will not update C
177 * - The above is however not a problem, because we also don't do that
178 * fancy "no flush" variant of eviction and we use H_REMOVE which will
179 * do the right thing and thus we don't have the race I described earlier
181 * - Under bare metal, we do have the race, so we need R and C set
182 * - We make sure R is always set and never lost
183 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
185 unsigned long htab_convert_pte_flags(unsigned long pteflags)
187 unsigned long rflags = 0;
189 /* _PAGE_EXEC -> NOEXEC */
190 if ((pteflags & _PAGE_EXEC) == 0)
194 * Linux uses slb key 0 for kernel and 1 for user.
195 * kernel RW areas are mapped with PPP=0b000
196 * User area is mapped with PPP=0b010 for read/write
197 * or PPP=0b011 for read-only (including writeable but clean pages).
199 if (pteflags & _PAGE_PRIVILEGED) {
201 * Kernel read only mapped with ppp bits 0b110
203 if (!(pteflags & _PAGE_WRITE)) {
204 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
205 rflags |= (HPTE_R_PP0 | 0x2);
210 if (pteflags & _PAGE_RWX)
212 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
216 * We can't allow hardware to update hpte bits. Hence always
217 * set 'R' bit and set 'C' if it is a write fault
221 if (pteflags & _PAGE_DIRTY)
227 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
229 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
230 rflags |= (HPTE_R_I | HPTE_R_G);
231 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
232 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
235 * Add memory coherence if cache inhibited is not set
239 rflags |= pte_to_hpte_pkey_bits(pteflags);
243 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
244 unsigned long pstart, unsigned long prot,
245 int psize, int ssize)
247 unsigned long vaddr, paddr;
248 unsigned int step, shift;
251 shift = mmu_psize_defs[psize].shift;
254 prot = htab_convert_pte_flags(prot);
256 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
257 vstart, vend, pstart, prot, psize, ssize);
259 for (vaddr = vstart, paddr = pstart; vaddr < vend;
260 vaddr += step, paddr += step) {
261 unsigned long hash, hpteg;
262 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
263 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
264 unsigned long tprot = prot;
267 * If we hit a bad address return error.
271 /* Make kernel text executable */
272 if (overlaps_kernel_text(vaddr, vaddr + step))
275 /* Make kvm guest trampolines executable */
276 if (overlaps_kvm_tmp(vaddr, vaddr + step))
280 * If relocatable, check if it overlaps interrupt vectors that
281 * are copied down to real 0. For relocatable kernel
282 * (e.g. kdump case) we copy interrupt vectors down to real
283 * address 0. Mark that region as executable. This is
284 * because on p8 system with relocation on exception feature
285 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
286 * in order to execute the interrupt handlers in virtual
287 * mode the vector region need to be marked as executable.
289 if ((PHYSICAL_START > MEMORY_START) &&
290 overlaps_interrupt_vector_text(vaddr, vaddr + step))
293 hash = hpt_hash(vpn, shift, ssize);
294 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
296 BUG_ON(!mmu_hash_ops.hpte_insert);
297 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
298 HPTE_V_BOLTED, psize, psize,
304 #ifdef CONFIG_DEBUG_PAGEALLOC
305 if (debug_pagealloc_enabled() &&
306 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
307 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
308 #endif /* CONFIG_DEBUG_PAGEALLOC */
310 return ret < 0 ? ret : 0;
313 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
314 int psize, int ssize)
317 unsigned int step, shift;
321 shift = mmu_psize_defs[psize].shift;
324 if (!mmu_hash_ops.hpte_removebolted)
327 for (vaddr = vstart; vaddr < vend; vaddr += step) {
328 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
340 static bool disable_1tb_segments = false;
342 static int __init parse_disable_1tb_segments(char *p)
344 disable_1tb_segments = true;
347 early_param("disable_1tb_segments", parse_disable_1tb_segments);
349 static int __init htab_dt_scan_seg_sizes(unsigned long node,
350 const char *uname, int depth,
353 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
357 /* We are scanning "cpu" nodes only */
358 if (type == NULL || strcmp(type, "cpu") != 0)
361 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
364 for (; size >= 4; size -= 4, ++prop) {
365 if (be32_to_cpu(prop[0]) == 40) {
366 DBG("1T segment support detected\n");
368 if (disable_1tb_segments) {
369 DBG("1T segments disabled by command line\n");
373 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
377 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
381 static int __init get_idx_from_shift(unsigned int shift)
405 static int __init htab_dt_scan_page_sizes(unsigned long node,
406 const char *uname, int depth,
409 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
413 /* We are scanning "cpu" nodes only */
414 if (type == NULL || strcmp(type, "cpu") != 0)
417 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
421 pr_info("Page sizes from device-tree:\n");
423 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
425 unsigned int base_shift = be32_to_cpu(prop[0]);
426 unsigned int slbenc = be32_to_cpu(prop[1]);
427 unsigned int lpnum = be32_to_cpu(prop[2]);
428 struct mmu_psize_def *def;
431 size -= 3; prop += 3;
432 base_idx = get_idx_from_shift(base_shift);
434 /* skip the pte encoding also */
435 prop += lpnum * 2; size -= lpnum * 2;
438 def = &mmu_psize_defs[base_idx];
439 if (base_idx == MMU_PAGE_16M)
440 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
442 def->shift = base_shift;
443 if (base_shift <= 23)
446 def->avpnm = (1 << (base_shift - 23)) - 1;
449 * We don't know for sure what's up with tlbiel, so
450 * for now we only set it for 4K and 64K pages
452 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
457 while (size > 0 && lpnum) {
458 unsigned int shift = be32_to_cpu(prop[0]);
459 int penc = be32_to_cpu(prop[1]);
461 prop += 2; size -= 2;
464 idx = get_idx_from_shift(shift);
469 pr_err("Invalid penc for base_shift=%d "
470 "shift=%d\n", base_shift, shift);
472 def->penc[idx] = penc;
473 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
474 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
475 base_shift, shift, def->sllp,
476 def->avpnm, def->tlbiel, def->penc[idx]);
483 #ifdef CONFIG_HUGETLB_PAGE
485 * Scan for 16G memory blocks that have been set aside for huge pages
486 * and reserve those blocks for 16G huge pages.
488 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
489 const char *uname, int depth,
491 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
492 const __be64 *addr_prop;
493 const __be32 *page_count_prop;
494 unsigned int expected_pages;
495 long unsigned int phys_addr;
496 long unsigned int block_size;
498 /* We are scanning "memory" nodes only */
499 if (type == NULL || strcmp(type, "memory") != 0)
503 * This property is the log base 2 of the number of virtual pages that
504 * will represent this memory block.
506 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
507 if (page_count_prop == NULL)
509 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
510 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
511 if (addr_prop == NULL)
513 phys_addr = be64_to_cpu(addr_prop[0]);
514 block_size = be64_to_cpu(addr_prop[1]);
515 if (block_size != (16 * GB))
517 printk(KERN_INFO "Huge page(16GB) memory: "
518 "addr = 0x%lX size = 0x%lX pages = %d\n",
519 phys_addr, block_size, expected_pages);
520 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
521 memblock_reserve(phys_addr, block_size * expected_pages);
522 pseries_add_gpage(phys_addr, block_size, expected_pages);
526 #endif /* CONFIG_HUGETLB_PAGE */
528 static void mmu_psize_set_default_penc(void)
531 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
532 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
533 mmu_psize_defs[bpsize].penc[apsize] = -1;
536 #ifdef CONFIG_PPC_64K_PAGES
538 static bool might_have_hea(void)
541 * The HEA ethernet adapter requires awareness of the
542 * GX bus. Without that awareness we can easily assume
543 * we will never see an HEA ethernet device.
545 #ifdef CONFIG_IBMEBUS
546 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
547 firmware_has_feature(FW_FEATURE_SPLPAR);
553 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
555 static void __init htab_scan_page_sizes(void)
559 /* se the invalid penc to -1 */
560 mmu_psize_set_default_penc();
562 /* Default to 4K pages only */
563 memcpy(mmu_psize_defs, mmu_psize_defaults,
564 sizeof(mmu_psize_defaults));
567 * Try to find the available page sizes in the device-tree
569 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
570 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
572 * Nothing in the device-tree, but the CPU supports 16M pages,
573 * so let's fallback on a known size list for 16M capable CPUs.
575 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
576 sizeof(mmu_psize_defaults_gp));
579 #ifdef CONFIG_HUGETLB_PAGE
580 if (!hugetlb_disabled) {
581 /* Reserve 16G huge page memory sections for huge pages */
582 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
584 #endif /* CONFIG_HUGETLB_PAGE */
588 * Fill in the hpte_page_sizes[] array.
589 * We go through the mmu_psize_defs[] array looking for all the
590 * supported base/actual page size combinations. Each combination
591 * has a unique pagesize encoding (penc) value in the low bits of
592 * the LP field of the HPTE. For actual page sizes less than 1MB,
593 * some of the upper LP bits are used for RPN bits, meaning that
594 * we need to fill in several entries in hpte_page_sizes[].
596 * In diagrammatic form, with r = RPN bits and z = page size bits:
597 * PTE LP actual page size
604 * The zzzz bits are implementation-specific but are chosen so that
605 * no encoding for a larger page size uses the same value in its
606 * low-order N bits as the encoding for the 2^(12+N) byte page size
609 static void init_hpte_page_sizes(void)
612 long int shift, penc;
614 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
615 if (!mmu_psize_defs[bp].shift)
616 continue; /* not a supported page size */
617 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
618 penc = mmu_psize_defs[bp].penc[ap];
619 if (penc == -1 || !mmu_psize_defs[ap].shift)
621 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
623 continue; /* should never happen */
625 * For page sizes less than 1MB, this loop
626 * replicates the entry for all possible values
629 while (penc < (1 << LP_BITS)) {
630 hpte_page_sizes[penc] = (ap << 4) | bp;
637 static void __init htab_init_page_sizes(void)
639 init_hpte_page_sizes();
641 if (!debug_pagealloc_enabled()) {
643 * Pick a size for the linear mapping. Currently, we only
644 * support 16M, 1M and 4K which is the default
646 if (mmu_psize_defs[MMU_PAGE_16M].shift)
647 mmu_linear_psize = MMU_PAGE_16M;
648 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
649 mmu_linear_psize = MMU_PAGE_1M;
652 #ifdef CONFIG_PPC_64K_PAGES
654 * Pick a size for the ordinary pages. Default is 4K, we support
655 * 64K for user mappings and vmalloc if supported by the processor.
656 * We only use 64k for ioremap if the processor
657 * (and firmware) support cache-inhibited large pages.
658 * If not, we use 4k and set mmu_ci_restrictions so that
659 * hash_page knows to switch processes that use cache-inhibited
660 * mappings to 4k pages.
662 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
663 mmu_virtual_psize = MMU_PAGE_64K;
664 mmu_vmalloc_psize = MMU_PAGE_64K;
665 if (mmu_linear_psize == MMU_PAGE_4K)
666 mmu_linear_psize = MMU_PAGE_64K;
667 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
669 * When running on pSeries using 64k pages for ioremap
670 * would stop us accessing the HEA ethernet. So if we
671 * have the chance of ever seeing one, stay at 4k.
673 if (!might_have_hea())
674 mmu_io_psize = MMU_PAGE_64K;
676 mmu_ci_restrictions = 1;
678 #endif /* CONFIG_PPC_64K_PAGES */
680 #ifdef CONFIG_SPARSEMEM_VMEMMAP
682 * We try to use 16M pages for vmemmap if that is supported
683 * and we have at least 1G of RAM at boot
685 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
686 memblock_phys_mem_size() >= 0x40000000)
687 mmu_vmemmap_psize = MMU_PAGE_16M;
689 mmu_vmemmap_psize = mmu_virtual_psize;
690 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
692 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
693 "virtual = %d, io = %d"
694 #ifdef CONFIG_SPARSEMEM_VMEMMAP
698 mmu_psize_defs[mmu_linear_psize].shift,
699 mmu_psize_defs[mmu_virtual_psize].shift,
700 mmu_psize_defs[mmu_io_psize].shift
701 #ifdef CONFIG_SPARSEMEM_VMEMMAP
702 ,mmu_psize_defs[mmu_vmemmap_psize].shift
707 static int __init htab_dt_scan_pftsize(unsigned long node,
708 const char *uname, int depth,
711 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
714 /* We are scanning "cpu" nodes only */
715 if (type == NULL || strcmp(type, "cpu") != 0)
718 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
720 /* pft_size[0] is the NUMA CEC cookie */
721 ppc64_pft_size = be32_to_cpu(prop[1]);
727 unsigned htab_shift_for_mem_size(unsigned long mem_size)
729 unsigned memshift = __ilog2(mem_size);
730 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
733 /* round mem_size up to next power of 2 */
734 if ((1UL << memshift) < mem_size)
737 /* aim for 2 pages / pteg */
738 pteg_shift = memshift - (pshift + 1);
741 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
742 * size permitted by the architecture.
744 return max(pteg_shift + 7, 18U);
747 static unsigned long __init htab_get_table_size(void)
750 * If hash size isn't already provided by the platform, we try to
751 * retrieve it from the device-tree. If it's not there neither, we
752 * calculate it now based on the total RAM size
754 if (ppc64_pft_size == 0)
755 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
757 return 1UL << ppc64_pft_size;
759 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
762 #ifdef CONFIG_MEMORY_HOTPLUG
763 int resize_hpt_for_hotplug(unsigned long new_mem_size)
765 unsigned target_hpt_shift;
767 if (!mmu_hash_ops.resize_hpt)
770 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
773 * To avoid lots of HPT resizes if memory size is fluctuating
774 * across a boundary, we deliberately have some hysterisis
775 * here: we immediately increase the HPT size if the target
776 * shift exceeds the current shift, but we won't attempt to
777 * reduce unless the target shift is at least 2 below the
780 if (target_hpt_shift > ppc64_pft_size ||
781 target_hpt_shift < ppc64_pft_size - 1)
782 return mmu_hash_ops.resize_hpt(target_hpt_shift);
787 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
791 if (end >= H_VMALLOC_START) {
792 pr_warn("Outside the supported range\n");
796 rc = htab_bolt_mapping(start, end, __pa(start),
797 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
801 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
803 BUG_ON(rc2 && (rc2 != -ENOENT));
808 int hash__remove_section_mapping(unsigned long start, unsigned long end)
810 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
815 #endif /* CONFIG_MEMORY_HOTPLUG */
817 static void __init hash_init_partition_table(phys_addr_t hash_table,
818 unsigned long htab_size)
820 mmu_partition_table_init();
823 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
824 * For now, UPRT is 0 and we have no segment table.
826 htab_size = __ilog2(htab_size) - 18;
827 mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
828 pr_info("Partition table %p\n", partition_tb);
831 static void __init htab_initialize(void)
834 unsigned long pteg_count;
836 unsigned long base = 0, size = 0;
837 struct memblock_region *reg;
839 DBG(" -> htab_initialize()\n");
841 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
842 mmu_kernel_ssize = MMU_SEGSIZE_1T;
843 mmu_highuser_ssize = MMU_SEGSIZE_1T;
844 printk(KERN_INFO "Using 1TB segments\n");
848 * Calculate the required size of the htab. We want the number of
849 * PTEGs to equal one half the number of real pages.
851 htab_size_bytes = htab_get_table_size();
852 pteg_count = htab_size_bytes >> 7;
854 htab_hash_mask = pteg_count - 1;
856 if (firmware_has_feature(FW_FEATURE_LPAR) ||
857 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
858 /* Using a hypervisor which owns the htab */
862 * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall
863 * to inform the hypervisor that we wish to use the HPT.
865 if (cpu_has_feature(CPU_FTR_ARCH_300))
866 register_process_table(0, 0, 0);
867 #ifdef CONFIG_FA_DUMP
869 * If firmware assisted dump is active firmware preserves
870 * the contents of htab along with entire partition memory.
871 * Clear the htab if firmware assisted dump is active so
872 * that we dont end up using old mappings.
874 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
875 mmu_hash_ops.hpte_clear_all();
878 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
880 #ifdef CONFIG_PPC_CELL
882 * Cell may require the hash table down low when using the
883 * Axon IOMMU in order to fit the dynamic region over it, see
884 * comments in cell/iommu.c
886 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
888 pr_info("Hash table forced below 2G for Axon IOMMU\n");
890 #endif /* CONFIG_PPC_CELL */
892 table = memblock_phys_alloc_range(htab_size_bytes,
896 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
897 &htab_size_bytes, &limit);
899 DBG("Hash table allocated at %lx, size: %lx\n", table,
902 htab_address = __va(table);
904 /* htab absolute addr + encoded htabsize */
905 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
907 /* Initialize the HPT with no entries */
908 memset((void *)table, 0, htab_size_bytes);
910 if (!cpu_has_feature(CPU_FTR_ARCH_300))
912 mtspr(SPRN_SDR1, _SDR1);
914 hash_init_partition_table(table, htab_size_bytes);
917 prot = pgprot_val(PAGE_KERNEL);
919 #ifdef CONFIG_DEBUG_PAGEALLOC
920 if (debug_pagealloc_enabled()) {
921 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
922 linear_map_hash_slots = memblock_alloc_try_nid(
923 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
924 ppc64_rma_size, NUMA_NO_NODE);
925 if (!linear_map_hash_slots)
926 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
927 __func__, linear_map_hash_count, &ppc64_rma_size);
929 #endif /* CONFIG_DEBUG_PAGEALLOC */
931 /* create bolted the linear mapping in the hash table */
932 for_each_memblock(memory, reg) {
933 base = (unsigned long)__va(reg->base);
936 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
939 if ((base + size) >= H_VMALLOC_START) {
940 pr_warn("Outside the supported range\n");
944 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
945 prot, mmu_linear_psize, mmu_kernel_ssize));
947 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
950 * If we have a memory_limit and we've allocated TCEs then we need to
951 * explicitly map the TCE area at the top of RAM. We also cope with the
952 * case that the TCEs start below memory_limit.
953 * tce_alloc_start/end are 16MB aligned so the mapping should work
954 * for either 4K or 16MB pages.
956 if (tce_alloc_start) {
957 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
958 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
960 if (base + size >= tce_alloc_start)
961 tce_alloc_start = base + size + 1;
963 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
964 __pa(tce_alloc_start), prot,
965 mmu_linear_psize, mmu_kernel_ssize));
969 DBG(" <- htab_initialize()\n");
974 void __init hash__early_init_devtree(void)
976 /* Initialize segment sizes */
977 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
979 /* Initialize page sizes */
980 htab_scan_page_sizes();
983 static struct hash_mm_context init_hash_mm_context;
984 void __init hash__early_init_mmu(void)
986 #ifndef CONFIG_PPC_64K_PAGES
988 * We have code in __hash_page_4K() and elsewhere, which assumes it can
990 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
992 * Where the slot number is between 0-15, and values of 8-15 indicate
993 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
994 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
995 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
996 * with a BUILD_BUG_ON().
998 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
999 #endif /* CONFIG_PPC_64K_PAGES */
1001 htab_init_page_sizes();
1004 * initialize page table size
1006 __pte_frag_nr = H_PTE_FRAG_NR;
1007 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1008 __pmd_frag_nr = H_PMD_FRAG_NR;
1009 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1011 __pte_index_size = H_PTE_INDEX_SIZE;
1012 __pmd_index_size = H_PMD_INDEX_SIZE;
1013 __pud_index_size = H_PUD_INDEX_SIZE;
1014 __pgd_index_size = H_PGD_INDEX_SIZE;
1015 __pud_cache_index = H_PUD_CACHE_INDEX;
1016 __pte_table_size = H_PTE_TABLE_SIZE;
1017 __pmd_table_size = H_PMD_TABLE_SIZE;
1018 __pud_table_size = H_PUD_TABLE_SIZE;
1019 __pgd_table_size = H_PGD_TABLE_SIZE;
1021 * 4k use hugepd format, so for hash set then to
1024 __pmd_val_bits = HASH_PMD_VAL_BITS;
1025 __pud_val_bits = HASH_PUD_VAL_BITS;
1026 __pgd_val_bits = HASH_PGD_VAL_BITS;
1028 __kernel_virt_start = H_KERN_VIRT_START;
1029 __vmalloc_start = H_VMALLOC_START;
1030 __vmalloc_end = H_VMALLOC_END;
1031 __kernel_io_start = H_KERN_IO_START;
1032 __kernel_io_end = H_KERN_IO_END;
1033 vmemmap = (struct page *)H_VMEMMAP_START;
1034 ioremap_bot = IOREMAP_BASE;
1037 pci_io_base = ISA_IO_BASE;
1040 /* Select appropriate backend */
1041 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1042 ps3_early_mm_init();
1043 else if (firmware_has_feature(FW_FEATURE_LPAR))
1044 hpte_init_pseries();
1045 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1048 if (!mmu_hash_ops.hpte_insert)
1049 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1052 * Initialize the MMU Hash table and create the linear mapping
1053 * of memory. Has to be done before SLB initialization as this is
1054 * currently where the page size encoding is obtained.
1058 init_mm.context.hash_context = &init_hash_mm_context;
1059 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1061 pr_info("Initializing hash mmu with SLB\n");
1062 /* Initialize SLB management */
1065 if (cpu_has_feature(CPU_FTR_ARCH_206)
1066 && cpu_has_feature(CPU_FTR_HVMODE))
1071 void hash__early_init_mmu_secondary(void)
1073 /* Initialize hash table for that CPU */
1074 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1076 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1077 mtspr(SPRN_SDR1, _SDR1);
1080 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1082 /* Initialize SLB */
1085 if (cpu_has_feature(CPU_FTR_ARCH_206)
1086 && cpu_has_feature(CPU_FTR_HVMODE))
1089 #endif /* CONFIG_SMP */
1092 * Called by asm hashtable.S for doing lazy icache flush
1094 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1098 if (!pfn_valid(pte_pfn(pte)))
1101 page = pte_page(pte);
1104 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1105 if (trap == 0x400) {
1106 flush_dcache_icache_page(page);
1107 set_bit(PG_arch_1, &page->flags);
1114 #ifdef CONFIG_PPC_MM_SLICES
1115 static unsigned int get_paca_psize(unsigned long addr)
1117 unsigned char *psizes;
1118 unsigned long index, mask_index;
1120 if (addr < SLICE_LOW_TOP) {
1121 psizes = get_paca()->mm_ctx_low_slices_psize;
1122 index = GET_LOW_SLICE_INDEX(addr);
1124 psizes = get_paca()->mm_ctx_high_slices_psize;
1125 index = GET_HIGH_SLICE_INDEX(addr);
1127 mask_index = index & 0x1;
1128 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1132 unsigned int get_paca_psize(unsigned long addr)
1134 return get_paca()->mm_ctx_user_psize;
1139 * Demote a segment to using 4k pages.
1140 * For now this makes the whole process use 4k pages.
1142 #ifdef CONFIG_PPC_64K_PAGES
1143 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1145 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1147 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1148 copro_flush_all_slbs(mm);
1149 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1151 copy_mm_to_paca(mm);
1152 slb_flush_and_restore_bolted();
1155 #endif /* CONFIG_PPC_64K_PAGES */
1157 #ifdef CONFIG_PPC_SUBPAGE_PROT
1159 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1160 * Userspace sets the subpage permissions using the subpage_prot system call.
1162 * Result is 0: full permissions, _PAGE_RW: read-only,
1163 * _PAGE_RWX: no access.
1165 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1167 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1174 if (ea >= spt->maxaddr)
1176 if (ea < 0x100000000UL) {
1177 /* addresses below 4GB use spt->low_prot */
1178 sbpm = spt->low_prot;
1180 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1184 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1187 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1189 /* extract 2-bit bitfield for this 4k subpage */
1190 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1193 * 0 -> full premission
1196 * We return the flag that need to be cleared.
1198 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1202 #else /* CONFIG_PPC_SUBPAGE_PROT */
1203 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1209 void hash_failure_debug(unsigned long ea, unsigned long access,
1210 unsigned long vsid, unsigned long trap,
1211 int ssize, int psize, int lpsize, unsigned long pte)
1213 if (!printk_ratelimit())
1215 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1216 ea, access, current->comm);
1217 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1218 trap, vsid, ssize, psize, lpsize, pte);
1221 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1222 int psize, bool user_region)
1225 if (psize != get_paca_psize(ea)) {
1226 copy_mm_to_paca(mm);
1227 slb_flush_and_restore_bolted();
1229 } else if (get_paca()->vmalloc_sllp !=
1230 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1231 get_paca()->vmalloc_sllp =
1232 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1233 slb_vmalloc_update();
1240 * 1 - normal page fault
1241 * -1 - critical hash insertion error
1242 * -2 - access not permitted by subpage protection mechanism
1244 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1245 unsigned long access, unsigned long trap,
1246 unsigned long flags)
1249 enum ctx_state prev_state = exception_enter();
1254 int rc, user_region = 0;
1257 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1259 trace_hash_fault(ea, access, trap);
1261 /* Get region & vsid */
1262 switch (get_region_id(ea)) {
1263 case USER_REGION_ID:
1266 DBG_LOW(" user region with no mm !\n");
1270 psize = get_slice_psize(mm, ea);
1271 ssize = user_segment_size(ea);
1272 vsid = get_user_vsid(&mm->context, ea, ssize);
1274 case VMALLOC_REGION_ID:
1275 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1276 psize = mmu_vmalloc_psize;
1277 ssize = mmu_kernel_ssize;
1281 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1282 psize = mmu_io_psize;
1283 ssize = mmu_kernel_ssize;
1288 * Send the problem up to do_page_fault()
1293 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1297 DBG_LOW("Bad address!\n");
1303 if (pgdir == NULL) {
1308 /* Check CPU locality */
1309 if (user_region && mm_is_thread_local(mm))
1310 flags |= HPTE_LOCAL_UPDATE;
1312 #ifndef CONFIG_PPC_64K_PAGES
1314 * If we use 4K pages and our psize is not 4K, then we might
1315 * be hitting a special driver mapping, and need to align the
1316 * address before we fetch the PTE.
1318 * It could also be a hugepage mapping, in which case this is
1319 * not necessary, but it's not harmful, either.
1321 if (psize != MMU_PAGE_4K)
1322 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1323 #endif /* CONFIG_PPC_64K_PAGES */
1325 /* Get PTE and page size from page tables */
1326 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1327 if (ptep == NULL || !pte_present(*ptep)) {
1328 DBG_LOW(" no PTE !\n");
1333 /* Add _PAGE_PRESENT to the required access perm */
1334 access |= _PAGE_PRESENT;
1337 * Pre-check access permissions (will be re-checked atomically
1338 * in __hash_page_XX but this pre-check is a fast path
1340 if (!check_pte_access(access, pte_val(*ptep))) {
1341 DBG_LOW(" no access !\n");
1348 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1349 trap, flags, ssize, psize);
1350 #ifdef CONFIG_HUGETLB_PAGE
1352 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1353 flags, ssize, hugeshift, psize);
1357 * if we have hugeshift, and is not transhuge with
1358 * hugetlb disabled, something is really wrong.
1364 if (current->mm == mm)
1365 check_paca_psize(ea, mm, psize, user_region);
1370 #ifndef CONFIG_PPC_64K_PAGES
1371 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1373 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1374 pte_val(*(ptep + PTRS_PER_PTE)));
1376 /* Do actual hashing */
1377 #ifdef CONFIG_PPC_64K_PAGES
1378 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1379 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1380 demote_segment_4k(mm, ea);
1381 psize = MMU_PAGE_4K;
1385 * If this PTE is non-cacheable and we have restrictions on
1386 * using non cacheable large pages, then we switch to 4k
1388 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1390 demote_segment_4k(mm, ea);
1391 psize = MMU_PAGE_4K;
1392 } else if (ea < VMALLOC_END) {
1394 * some driver did a non-cacheable mapping
1395 * in vmalloc space, so switch vmalloc
1398 printk(KERN_ALERT "Reducing vmalloc segment "
1399 "to 4kB pages because of "
1400 "non-cacheable mapping\n");
1401 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1402 copro_flush_all_slbs(mm);
1406 #endif /* CONFIG_PPC_64K_PAGES */
1408 if (current->mm == mm)
1409 check_paca_psize(ea, mm, psize, user_region);
1411 #ifdef CONFIG_PPC_64K_PAGES
1412 if (psize == MMU_PAGE_64K)
1413 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1416 #endif /* CONFIG_PPC_64K_PAGES */
1418 int spp = subpage_protection(mm, ea);
1422 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1427 * Dump some info in case of hash insertion failure, they should
1428 * never happen so it is really useful to know if/when they do
1431 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1432 psize, pte_val(*ptep));
1433 #ifndef CONFIG_PPC_64K_PAGES
1434 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1436 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1437 pte_val(*(ptep + PTRS_PER_PTE)));
1439 DBG_LOW(" -> rc=%d\n", rc);
1442 exception_exit(prev_state);
1445 EXPORT_SYMBOL_GPL(hash_page_mm);
1447 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1448 unsigned long dsisr)
1450 unsigned long flags = 0;
1451 struct mm_struct *mm = current->mm;
1453 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1454 (get_region_id(ea) == IO_REGION_ID))
1457 if (dsisr & DSISR_NOHPTE)
1458 flags |= HPTE_NOHPTE_UPDATE;
1460 return hash_page_mm(mm, ea, access, trap, flags);
1462 EXPORT_SYMBOL_GPL(hash_page);
1464 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1465 unsigned long dsisr)
1467 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1468 unsigned long flags = 0;
1469 struct mm_struct *mm = current->mm;
1470 unsigned int region_id = get_region_id(ea);
1472 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1475 if (dsisr & DSISR_NOHPTE)
1476 flags |= HPTE_NOHPTE_UPDATE;
1478 if (dsisr & DSISR_ISSTORE)
1479 access |= _PAGE_WRITE;
1481 * We set _PAGE_PRIVILEGED only when
1482 * kernel mode access kernel space.
1484 * _PAGE_PRIVILEGED is NOT set
1485 * 1) when kernel mode access user space
1486 * 2) user space access kernel space.
1488 access |= _PAGE_PRIVILEGED;
1489 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1490 access &= ~_PAGE_PRIVILEGED;
1493 access |= _PAGE_EXEC;
1495 return hash_page_mm(mm, ea, access, trap, flags);
1498 #ifdef CONFIG_PPC_MM_SLICES
1499 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1501 int psize = get_slice_psize(mm, ea);
1503 /* We only prefault standard pages for now */
1504 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1508 * Don't prefault if subpage protection is enabled for the EA.
1510 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1516 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1522 void hash_preload(struct mm_struct *mm, unsigned long ea,
1523 bool is_exec, unsigned long trap)
1529 unsigned long flags;
1530 int rc, ssize, update_flags = 0;
1531 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1533 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1535 if (!should_hash_preload(mm, ea))
1538 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1539 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1541 /* Get Linux PTE if available */
1547 ssize = user_segment_size(ea);
1548 vsid = get_user_vsid(&mm->context, ea, ssize);
1552 * Hash doesn't like irqs. Walking linux page table with irq disabled
1553 * saves us from holding multiple locks.
1555 local_irq_save(flags);
1558 * THP pages use update_mmu_cache_pmd. We don't do
1559 * hash preload there. Hence can ignore THP here
1561 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1565 WARN_ON(hugepage_shift);
1566 #ifdef CONFIG_PPC_64K_PAGES
1567 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1568 * a 64K kernel), then we don't preload, hash_page() will take
1569 * care of it once we actually try to access the page.
1570 * That way we don't have to duplicate all of the logic for segment
1571 * page size demotion here
1573 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1575 #endif /* CONFIG_PPC_64K_PAGES */
1577 /* Is that local to this CPU ? */
1578 if (mm_is_thread_local(mm))
1579 update_flags |= HPTE_LOCAL_UPDATE;
1582 #ifdef CONFIG_PPC_64K_PAGES
1583 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1584 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1585 update_flags, ssize);
1587 #endif /* CONFIG_PPC_64K_PAGES */
1588 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1589 ssize, subpage_protection(mm, ea));
1591 /* Dump some info in case of hash insertion failure, they should
1592 * never happen so it is really useful to know if/when they do
1595 hash_failure_debug(ea, access, vsid, trap, ssize,
1596 mm_ctx_user_psize(&mm->context),
1597 mm_ctx_user_psize(&mm->context),
1600 local_irq_restore(flags);
1603 #ifdef CONFIG_PPC_MEM_KEYS
1605 * Return the protection key associated with the given address and the
1608 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1612 unsigned long flags;
1614 if (!mm || !mm->pgd)
1617 local_irq_save(flags);
1618 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1620 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1621 local_irq_restore(flags);
1625 #endif /* CONFIG_PPC_MEM_KEYS */
1627 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1628 static inline void tm_flush_hash_page(int local)
1631 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1632 * page back to a block device w/PIO could pick up transactional data
1633 * (bad!) so we force an abort here. Before the sync the page will be
1634 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1635 * kernel uses a page from userspace without unmapping it first, it may
1636 * see the speculated version.
1638 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1639 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1641 tm_abort(TM_CAUSE_TLBI);
1645 static inline void tm_flush_hash_page(int local)
1651 * Return the global hash slot, corresponding to the given PTE, which contains
1654 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1655 int ssize, real_pte_t rpte, unsigned int subpg_index)
1657 unsigned long hash, gslot, hidx;
1659 hash = hpt_hash(vpn, shift, ssize);
1660 hidx = __rpte_to_hidx(rpte, subpg_index);
1661 if (hidx & _PTEIDX_SECONDARY)
1663 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1664 gslot += hidx & _PTEIDX_GROUP_IX;
1669 * WARNING: This is called from hash_low_64.S, if you change this prototype,
1670 * do not forget to update the assembly call site !
1672 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1673 unsigned long flags)
1675 unsigned long index, shift, gslot;
1676 int local = flags & HPTE_LOCAL_UPDATE;
1678 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1679 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1680 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1681 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1683 * We use same base page size and actual psize, because we don't
1684 * use these functions for hugepage
1686 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1688 } pte_iterate_hashed_end();
1690 tm_flush_hash_page(local);
1693 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1694 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1695 pmd_t *pmdp, unsigned int psize, int ssize,
1696 unsigned long flags)
1698 int i, max_hpte_count, valid;
1699 unsigned long s_addr;
1700 unsigned char *hpte_slot_array;
1701 unsigned long hidx, shift, vpn, hash, slot;
1702 int local = flags & HPTE_LOCAL_UPDATE;
1704 s_addr = addr & HPAGE_PMD_MASK;
1705 hpte_slot_array = get_hpte_slot_array(pmdp);
1707 * IF we try to do a HUGE PTE update after a withdraw is done.
1708 * we will find the below NULL. This happens when we do
1709 * split_huge_page_pmd
1711 if (!hpte_slot_array)
1714 if (mmu_hash_ops.hugepage_invalidate) {
1715 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1716 psize, ssize, local);
1720 * No bluk hpte removal support, invalidate each entry
1722 shift = mmu_psize_defs[psize].shift;
1723 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1724 for (i = 0; i < max_hpte_count; i++) {
1726 * 8 bits per each hpte entries
1727 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1729 valid = hpte_valid(hpte_slot_array, i);
1732 hidx = hpte_hash_index(hpte_slot_array, i);
1735 addr = s_addr + (i * (1ul << shift));
1736 vpn = hpt_vpn(addr, vsid, ssize);
1737 hash = hpt_hash(vpn, shift, ssize);
1738 if (hidx & _PTEIDX_SECONDARY)
1741 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1742 slot += hidx & _PTEIDX_GROUP_IX;
1743 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1744 MMU_PAGE_16M, ssize, local);
1747 tm_flush_hash_page(local);
1749 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1751 void flush_hash_range(unsigned long number, int local)
1753 if (mmu_hash_ops.flush_hash_range)
1754 mmu_hash_ops.flush_hash_range(number, local);
1757 struct ppc64_tlb_batch *batch =
1758 this_cpu_ptr(&ppc64_tlb_batch);
1760 for (i = 0; i < number; i++)
1761 flush_hash_page(batch->vpn[i], batch->pte[i],
1762 batch->psize, batch->ssize, local);
1767 * low_hash_fault is called when we the low level hash code failed
1768 * to instert a PTE due to an hypervisor error
1770 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1772 enum ctx_state prev_state = exception_enter();
1774 if (user_mode(regs)) {
1775 #ifdef CONFIG_PPC_SUBPAGE_PROT
1777 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1780 _exception(SIGBUS, regs, BUS_ADRERR, address);
1782 bad_page_fault(regs, address, SIGBUS);
1784 exception_exit(prev_state);
1787 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1788 unsigned long pa, unsigned long rflags,
1789 unsigned long vflags, int psize, int ssize)
1791 unsigned long hpte_group;
1795 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1797 /* Insert into the hash table, primary slot */
1798 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1799 psize, psize, ssize);
1801 /* Primary is full, try the secondary */
1802 if (unlikely(slot == -1)) {
1803 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1804 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1805 vflags | HPTE_V_SECONDARY,
1806 psize, psize, ssize);
1809 hpte_group = (hash & htab_hash_mask) *
1812 mmu_hash_ops.hpte_remove(hpte_group);
1820 #ifdef CONFIG_DEBUG_PAGEALLOC
1821 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1824 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1825 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1826 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1829 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1831 /* Don't create HPTE entries for bad address */
1835 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1837 mmu_linear_psize, mmu_kernel_ssize);
1840 spin_lock(&linear_map_hash_lock);
1841 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1842 linear_map_hash_slots[lmi] = ret | 0x80;
1843 spin_unlock(&linear_map_hash_lock);
1846 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1848 unsigned long hash, hidx, slot;
1849 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1850 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1852 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1853 spin_lock(&linear_map_hash_lock);
1854 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1855 hidx = linear_map_hash_slots[lmi] & 0x7f;
1856 linear_map_hash_slots[lmi] = 0;
1857 spin_unlock(&linear_map_hash_lock);
1858 if (hidx & _PTEIDX_SECONDARY)
1860 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1861 slot += hidx & _PTEIDX_GROUP_IX;
1862 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1864 mmu_kernel_ssize, 0);
1867 void __kernel_map_pages(struct page *page, int numpages, int enable)
1869 unsigned long flags, vaddr, lmi;
1872 local_irq_save(flags);
1873 for (i = 0; i < numpages; i++, page++) {
1874 vaddr = (unsigned long)page_address(page);
1875 lmi = __pa(vaddr) >> PAGE_SHIFT;
1876 if (lmi >= linear_map_hash_count)
1879 kernel_map_linear_page(vaddr, lmi);
1881 kernel_unmap_linear_page(vaddr, lmi);
1883 local_irq_restore(flags);
1885 #endif /* CONFIG_DEBUG_PAGEALLOC */
1887 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1888 phys_addr_t first_memblock_size)
1891 * We don't currently support the first MEMBLOCK not mapping 0
1892 * physical on those processors
1894 BUG_ON(first_memblock_base != 0);
1897 * On virtualized systems the first entry is our RMA region aka VRMA,
1898 * non-virtualized 64-bit hash MMU systems don't have a limitation
1899 * on real mode access.
1901 * For guests on platforms before POWER9, we clamp the it limit to 1G
1902 * to avoid some funky things such as RTAS bugs etc...
1904 * On POWER9 we limit to 1TB in case the host erroneously told us that
1905 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1906 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1907 * for virtual real mode addressing and so it doesn't make sense to
1908 * have an area larger than 1TB as it can't be addressed.
1910 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1911 ppc64_rma_size = first_memblock_size;
1912 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1913 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1915 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1916 1UL << SID_SHIFT_1T);
1918 /* Finally limit subsequent allocations */
1919 memblock_set_current_limit(ppc64_rma_size);
1921 ppc64_rma_size = ULONG_MAX;
1925 #ifdef CONFIG_DEBUG_FS
1927 static int hpt_order_get(void *data, u64 *val)
1929 *val = ppc64_pft_size;
1933 static int hpt_order_set(void *data, u64 val)
1937 if (!mmu_hash_ops.resize_hpt)
1941 ret = mmu_hash_ops.resize_hpt(val);
1947 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1949 static int __init hash64_debugfs(void)
1951 if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root,
1952 NULL, &fops_hpt_order)) {
1953 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1958 machine_device_initcall(pseries, hash64_debugfs);
1959 #endif /* CONFIG_DEBUG_FS */
1961 void __init print_system_hash_info(void)
1963 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
1966 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
1967 pr_info("kernel vmalloc start = 0x%lx\n", KERN_VIRT_START);
1968 pr_info("kernel IO start = 0x%lx\n", KERN_IO_START);
1969 pr_info("kernel vmemmap start = 0x%lx\n", (unsigned long)vmemmap);