1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
4 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
10 #include <ppc_asm.tmpl>
13 #include <asm/cache.h>
15 /*------------------------------------------------------------------------------- */
16 /* Function: ppcDcbf */
17 /* Description: Data Cache block flush */
18 /* Input: r3 = effective address */
20 /*------------------------------------------------------------------------------- */
26 /*------------------------------------------------------------------------------- */
27 /* Function: ppcDcbi */
28 /* Description: Data Cache block Invalidate */
29 /* Input: r3 = effective address */
31 /*------------------------------------------------------------------------------- */
37 /*--------------------------------------------------------------------------
39 * Description: Data Cache block zero.
40 * Input: r3 = effective address
42 *-------------------------------------------------------------------------- */
49 /*------------------------------------------------------------------------------- */
50 /* Function: ppcSync */
51 /* Description: Processor Synchronize */
54 /*------------------------------------------------------------------------------- */
61 * Write any modified data cache blocks out to memory and invalidate them.
62 * Does not invalidate the corresponding instruction cache blocks.
64 * flush_dcache_range(unsigned long start, unsigned long stop)
66 _GLOBAL(flush_dcache_range)
67 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
68 li r5,L1_CACHE_BYTES-1
72 srwi. r4,r4,L1_CACHE_SHIFT
77 addi r3,r3,L1_CACHE_BYTES
79 sync /* wait for dcbst's to get to ram */
84 * Like above, but invalidate the D-cache. This is used by the 8xx
85 * to invalidate the cache so the PPC core doesn't get stale data
86 * from the CPM (no cache snooping here :-).
88 * invalidate_dcache_range(unsigned long start, unsigned long stop)
90 _GLOBAL(invalidate_dcache_range)
91 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
92 li r5,L1_CACHE_BYTES-1
96 srwi. r4,r4,L1_CACHE_SHIFT
102 addi r3,r3,L1_CACHE_BYTES
104 sync /* wait for dcbi's to get to ram */