2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
35 /* Sign-extend HDEC if not on POWER9 */
36 #define EXTEND_HDEC(reg) \
39 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
41 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
43 /* Values in HSTATE_NAPPING(r13) */
44 #define NAPPING_CEDE 1
45 #define NAPPING_NOVCPU 2
47 /* Stack frame offsets for kvmppc_hv_entry */
49 #define STACK_SLOT_TRAP (SFS-4)
50 #define STACK_SLOT_TID (SFS-16)
51 #define STACK_SLOT_PSSCR (SFS-24)
52 #define STACK_SLOT_PID (SFS-32)
53 #define STACK_SLOT_IAMR (SFS-40)
54 #define STACK_SLOT_CIABR (SFS-48)
55 #define STACK_SLOT_DAWR (SFS-56)
56 #define STACK_SLOT_DAWRX (SFS-64)
57 #define STACK_SLOT_HFSCR (SFS-72)
60 * Call kvmppc_hv_entry in real mode.
61 * Must be called with interrupts hard-disabled.
65 * LR = return address to continue at after eventually re-enabling MMU
67 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
69 std r0, PPC_LR_STKOFF(r1)
72 std r10, HSTATE_HOST_MSR(r13)
73 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
78 mtmsrd r0,1 /* clear RI in MSR */
84 ld r4, HSTATE_KVM_VCPU(r13)
87 /* Back from guest - restore host state and return to caller */
90 /* Restore host DABR and DABRX */
91 ld r5,HSTATE_DABR(r13)
95 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
98 ld r3,PACA_SPRG_VDSO(r13)
99 mtspr SPRN_SPRG_VDSO_WRITE,r3
101 /* Reload the host's PMU registers */
102 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
103 lbz r4, LPPACA_PMCINUSE(r3)
105 beq 23f /* skip if not */
107 ld r3, HSTATE_MMCR0(r13)
108 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
111 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
112 lwz r3, HSTATE_PMC1(r13)
113 lwz r4, HSTATE_PMC2(r13)
114 lwz r5, HSTATE_PMC3(r13)
115 lwz r6, HSTATE_PMC4(r13)
116 lwz r8, HSTATE_PMC5(r13)
117 lwz r9, HSTATE_PMC6(r13)
124 ld r3, HSTATE_MMCR0(r13)
125 ld r4, HSTATE_MMCR1(r13)
126 ld r5, HSTATE_MMCRA(r13)
127 ld r6, HSTATE_SIAR(r13)
128 ld r7, HSTATE_SDAR(r13)
134 ld r8, HSTATE_MMCR2(r13)
135 ld r9, HSTATE_SIER(r13)
138 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
144 * Reload DEC. HDEC interrupts were disabled when
145 * we reloaded the host's LPCR value.
147 ld r3, HSTATE_DECEXP(r13)
153 /* hwthread_req may have got set by cede or no vcpu, so clear it */
155 stb r0, HSTATE_HWTHREAD_REQ(r13)
156 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
159 * For external interrupts we need to call the Linux
160 * handler to process the interrupt. We do that by jumping
161 * to absolute address 0x500 for external interrupts.
162 * The [h]rfid at the end of the handler will return to
163 * the book3s_hv_interrupts.S code. For other interrupts
164 * we do the rfid to get back to the book3s_hv_interrupts.S
167 ld r8, 112+PPC_LR_STKOFF(r1)
169 ld r7, HSTATE_HOST_MSR(r13)
171 /* Return the trap number on this thread as the return value */
175 * If we came back from the guest via a relocation-on interrupt,
176 * we will be in virtual mode at this point, which makes it a
177 * little easier to get back to the caller.
180 andi. r0, r0, MSR_IR /* in real mode? */
183 /* RFI into the highmem handler */
187 mtmsrd r6, 1 /* Clear RI in MSR */
192 /* Virtual-mode return */
197 kvmppc_primary_no_guest:
198 /* We handle this much like a ceded vcpu */
199 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
200 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
201 /* HDEC value came from DEC in the first place, it will fit */
205 * Make sure the primary has finished the MMU switch.
206 * We should never get here on a secondary thread, but
207 * check it for robustness' sake.
209 ld r5, HSTATE_KVM_VCORE(r13)
210 65: lbz r0, VCORE_IN_GUEST(r5)
217 /* set our bit in napping_threads */
218 ld r5, HSTATE_KVM_VCORE(r13)
219 lbz r7, HSTATE_PTID(r13)
222 addi r6, r5, VCORE_NAPPING_THREADS
227 /* order napping_threads update vs testing entry_exit_map */
230 lwz r7, VCORE_ENTRY_EXIT(r5)
232 bge kvm_novcpu_exit /* another thread already exiting */
233 li r3, NAPPING_NOVCPU
234 stb r3, HSTATE_NAPPING(r13)
236 li r3, 0 /* Don't wake on privileged (OS) doorbell */
241 * Entered from kvm_start_guest if kvm_hstate.napping is set
247 ld r1, HSTATE_HOST_R1(r13)
248 ld r5, HSTATE_KVM_VCORE(r13)
250 stb r0, HSTATE_NAPPING(r13)
252 /* check the wake reason */
253 bl kvmppc_check_wake_reason
256 * Restore volatile registers since we could have called
257 * a C routine in kvmppc_check_wake_reason.
260 ld r5, HSTATE_KVM_VCORE(r13)
262 /* see if any other thread is already exiting */
263 lwz r0, VCORE_ENTRY_EXIT(r5)
267 /* clear our bit in napping_threads */
268 lbz r7, HSTATE_PTID(r13)
271 addi r6, r5, VCORE_NAPPING_THREADS
277 /* See if the wake reason means we need to exit */
281 /* See if our timeslice has expired (HDEC is negative) */
284 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
288 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
289 ld r4, HSTATE_KVM_VCPU(r13)
291 beq kvmppc_primary_no_guest
293 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
294 addi r3, r4, VCPU_TB_RMENTRY
295 bl kvmhv_start_timing
300 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
301 ld r4, HSTATE_KVM_VCPU(r13)
304 addi r3, r4, VCPU_TB_RMEXIT
305 bl kvmhv_accumulate_time
308 stw r12, STACK_SLOT_TRAP(r1)
309 bl kvmhv_commence_exit
311 lwz r12, STACK_SLOT_TRAP(r1)
312 b kvmhv_switch_to_host
315 * We come in here when wakened from nap mode.
316 * Relocation is off and most register values are lost.
317 * r13 points to the PACA.
318 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
319 * This is not used by ISAv3.0B processors.
321 .globl kvm_start_guest
323 /* Set runlatch bit the minute you wake up from nap */
329 * Could avoid this and pass it through in r3. For now,
330 * code expects it to be in SRR1.
336 li r0,KVM_HWTHREAD_IN_KVM
337 stb r0,HSTATE_HWTHREAD_STATE(r13)
339 /* NV GPR values from power7_idle() will no longer be valid */
341 stb r0,PACA_NAPSTATELOST(r13)
343 /* were we napping due to cede? */
344 lbz r0,HSTATE_NAPPING(r13)
345 cmpwi r0,NAPPING_CEDE
347 cmpwi r0,NAPPING_NOVCPU
348 beq kvm_novcpu_wakeup
350 ld r1,PACAEMERGSP(r13)
351 subi r1,r1,STACK_FRAME_OVERHEAD
354 * We weren't napping due to cede, so this must be a secondary
355 * thread being woken up to run a guest, or being woken up due
356 * to a stray IPI. (Or due to some machine check or hypervisor
357 * maintenance interrupt while the core is in KVM.)
360 /* Check the wake reason in SRR1 to see why we got here */
361 bl kvmppc_check_wake_reason
363 * kvmppc_check_wake_reason could invoke a C routine, but we
364 * have no volatile registers to restore when we return.
370 /* get vcore pointer, NULL if we have nothing to run */
371 ld r5,HSTATE_KVM_VCORE(r13)
373 /* if we have no vcore to run, go back to sleep */
376 kvm_secondary_got_guest:
378 /* Set HSTATE_DSCR(r13) to something sensible */
379 ld r6, PACA_DSCR_DEFAULT(r13)
380 std r6, HSTATE_DSCR(r13)
382 /* On thread 0 of a subcore, set HDEC to max */
383 lbz r4, HSTATE_PTID(r13)
386 LOAD_REG_ADDR(r6, decrementer_max)
389 /* and set per-LPAR registers, if doing dynamic micro-threading */
390 ld r6, HSTATE_SPLIT_MODE(r13)
393 ld r0, KVM_SPLIT_RPR(r6)
395 ld r0, KVM_SPLIT_PMMAR(r6)
397 ld r0, KVM_SPLIT_LDBAR(r6)
401 /* Order load of vcpu after load of vcore */
403 ld r4, HSTATE_KVM_VCPU(r13)
406 /* Back from the guest, go back to nap */
407 /* Clear our vcpu and vcore pointers so we don't come back in early */
409 std r0, HSTATE_KVM_VCPU(r13)
411 * Once we clear HSTATE_KVM_VCORE(r13), the code in
412 * kvmppc_run_core() is going to assume that all our vcpu
413 * state is visible in memory. This lwsync makes sure
417 std r0, HSTATE_KVM_VCORE(r13)
420 * All secondaries exiting guest will fall through this path.
421 * Before proceeding, just check for HMI interrupt and
422 * invoke opal hmi handler. By now we are sure that the
423 * primary thread on this core/subcore has already made partition
424 * switch/TB resync and we are good to call opal hmi handler.
426 cmpwi r12, BOOK3S_INTERRUPT_HMI
429 li r3,0 /* NULL argument */
430 bl hmi_exception_realmode
432 * At this point we have finished executing in the guest.
433 * We need to wait for hwthread_req to become zero, since
434 * we may not turn on the MMU while hwthread_req is non-zero.
435 * While waiting we also need to check if we get given a vcpu to run.
440 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
441 lbz r3, HSTATE_HWTHREAD_REQ(r13)
445 li r0, KVM_HWTHREAD_IN_KERNEL
446 stb r0, HSTATE_HWTHREAD_STATE(r13)
447 /* need to recheck hwthread_req after a barrier, to avoid race */
449 lbz r3, HSTATE_HWTHREAD_REQ(r13)
453 * We jump to pnv_wakeup_loss, which will return to the caller
454 * of power7_nap in the powernv cpu offline loop. The value we
455 * put in r3 becomes the return value for power7_nap. pnv_wakeup_loss
456 * requires SRR1 in r12.
460 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
467 ld r5, HSTATE_KVM_VCORE(r13)
470 ld r3, HSTATE_SPLIT_MODE(r13)
473 lbz r0, KVM_SPLIT_DO_NAP(r3)
479 b kvm_secondary_got_guest
481 54: li r0, KVM_HWTHREAD_IN_KVM
482 stb r0, HSTATE_HWTHREAD_STATE(r13)
486 * Here the primary thread is trying to return the core to
487 * whole-core mode, so we need to nap.
491 * When secondaries are napping in kvm_unsplit_nap() with
492 * hwthread_req = 1, HMI goes ignored even though subcores are
493 * already exited the guest. Hence HMI keeps waking up secondaries
494 * from nap in a loop and secondaries always go back to nap since
495 * no vcore is assigned to them. This makes impossible for primary
496 * thread to get hold of secondary threads resulting into a soft
497 * lockup in KVM path.
499 * Let us check if HMI is pending and handle it before we go to nap.
501 cmpwi r12, BOOK3S_INTERRUPT_HMI
503 li r3, 0 /* NULL argument */
504 bl hmi_exception_realmode
507 * Ensure that secondary doesn't nap when it has
508 * its vcore pointer set.
510 sync /* matches smp_mb() before setting split_info.do_nap */
511 ld r0, HSTATE_KVM_VCORE(r13)
514 /* clear any pending message */
516 lis r6, (PPC_DBELL_SERVER << (63-36))@h
518 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
519 /* Set kvm_split_mode.napped[tid] = 1 */
520 ld r3, HSTATE_SPLIT_MODE(r13)
522 lhz r4, PACAPACAINDEX(r13)
523 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
524 addi r4, r4, KVM_SPLIT_NAPPED
526 /* Check the do_nap flag again after setting napped[] */
528 lbz r0, KVM_SPLIT_DO_NAP(r3)
531 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
533 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
540 /******************************************************************************
544 *****************************************************************************/
546 .global kvmppc_hv_entry
551 * R4 = vcpu pointer (or NULL)
556 * all other volatile GPRS = free
557 * Does not preserve non-volatile GPRs or CR fields
560 std r0, PPC_LR_STKOFF(r1)
563 /* Save R1 in the PACA */
564 std r1, HSTATE_HOST_R1(r13)
566 li r6, KVM_GUEST_MODE_HOST_HV
567 stb r6, HSTATE_IN_GUEST(r13)
569 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
570 /* Store initial timestamp */
573 addi r3, r4, VCPU_TB_RMENTRY
574 bl kvmhv_start_timing
578 /* Use cr7 as an indication of radix mode */
579 ld r5, HSTATE_KVM_VCORE(r13)
580 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
581 lbz r0, KVM_RADIX(r9)
584 /* Clear out SLB if hash */
592 * POWER7/POWER8 host -> guest partition switch code.
593 * We don't have to lock against concurrent tlbies,
594 * but we do have to coordinate across hardware threads.
596 /* Set bit in entry map iff exit map is zero. */
598 lbz r6, HSTATE_PTID(r13)
600 addi r8, r5, VCORE_ENTRY_EXIT
602 cmpwi r3, 0x100 /* any threads starting to exit? */
603 bge secondary_too_late /* if so we're too late to the party */
608 /* Primary thread switches to guest partition. */
614 li r0,LPID_RSVD /* switch to reserved LPID */
617 mtspr SPRN_SDR1,r6 /* switch to partition page table */
618 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
622 /* See if we need to flush the TLB */
623 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
626 * On POWER9, individual threads can come in here, but the
627 * TLB is shared between the 4 threads in a core, hence
628 * invalidating on one thread invalidates for all.
629 * Thus we make all 4 threads use the same bit here.
632 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
633 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
634 srdi r6,r6,6 /* doubleword number */
635 sldi r6,r6,3 /* address offset */
637 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
643 /* Flush the TLB of any entries for this LPID */
644 lwz r0,KVM_TLB_SETS(r9)
646 li r7,0x800 /* IS field = 0b10 */
648 li r0,0 /* RS for P9 version of tlbiel */
650 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
654 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
658 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
663 /* Add timebase offset onto timebase */
664 22: ld r8,VCORE_TB_OFFSET(r5)
667 mftb r6 /* current host timebase */
669 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
670 mftb r7 /* check if lower 24 bits overflowed */
675 addis r8,r8,0x100 /* if so, increment upper 40 bits */
678 /* Load guest PCR value to select appropriate compat mode */
679 37: ld r7, VCORE_PCR(r5)
686 /* DPDES and VTB are shared between threads */
687 ld r8, VCORE_DPDES(r5)
691 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
693 /* Mark the subcore state as inside guest */
694 bl kvmppc_subcore_enter_guest
696 ld r5, HSTATE_KVM_VCORE(r13)
697 ld r4, HSTATE_KVM_VCPU(r13)
699 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
701 /* Do we have a guest vcpu to run? */
703 beq kvmppc_primary_no_guest
706 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
707 lwz r5,VCPU_SLB_MAX(r4)
712 1: ld r8,VCPU_SLB_E(r6)
715 addi r6,r6,VCPU_SLB_SIZE
718 /* Increment yield count if they have a VPA */
722 li r6, LPPACA_YIELDCOUNT
727 stb r6, VCPU_VPA_DIRTY(r4)
730 /* Save purr/spurr */
733 std r5,HSTATE_PURR(r13)
734 std r6,HSTATE_SPURR(r13)
740 /* Save host values of some registers */
746 std r5, STACK_SLOT_TID(r1)
747 std r6, STACK_SLOT_PSSCR(r1)
748 std r7, STACK_SLOT_PID(r1)
749 std r8, STACK_SLOT_IAMR(r1)
751 std r5, STACK_SLOT_HFSCR(r1)
752 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
757 std r5, STACK_SLOT_CIABR(r1)
758 std r6, STACK_SLOT_DAWR(r1)
759 std r7, STACK_SLOT_DAWRX(r1)
760 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
763 /* Set partition DABR */
764 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
765 lwz r5,VCPU_DABRX(r4)
770 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
772 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
775 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
778 END_FTR_SECTION_IFSET(CPU_FTR_TM)
781 /* Load guest PMU registers */
782 /* R4 is live here (vcpu pointer) */
784 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
785 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
789 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
792 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
793 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
794 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
795 lwz r6, VCPU_PMC + 8(r4)
796 lwz r7, VCPU_PMC + 12(r4)
797 lwz r8, VCPU_PMC + 16(r4)
798 lwz r9, VCPU_PMC + 20(r4)
806 ld r5, VCPU_MMCR + 8(r4)
807 ld r6, VCPU_MMCR + 16(r4)
815 ld r5, VCPU_MMCR + 24(r4)
819 BEGIN_FTR_SECTION_NESTED(96)
820 lwz r7, VCPU_PMC + 24(r4)
821 lwz r8, VCPU_PMC + 28(r4)
822 ld r9, VCPU_MMCR + 32(r4)
826 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
827 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
831 /* Load up FP, VMX and VSX registers */
834 ld r14, VCPU_GPR(R14)(r4)
835 ld r15, VCPU_GPR(R15)(r4)
836 ld r16, VCPU_GPR(R16)(r4)
837 ld r17, VCPU_GPR(R17)(r4)
838 ld r18, VCPU_GPR(R18)(r4)
839 ld r19, VCPU_GPR(R19)(r4)
840 ld r20, VCPU_GPR(R20)(r4)
841 ld r21, VCPU_GPR(R21)(r4)
842 ld r22, VCPU_GPR(R22)(r4)
843 ld r23, VCPU_GPR(R23)(r4)
844 ld r24, VCPU_GPR(R24)(r4)
845 ld r25, VCPU_GPR(R25)(r4)
846 ld r26, VCPU_GPR(R26)(r4)
847 ld r27, VCPU_GPR(R27)(r4)
848 ld r28, VCPU_GPR(R28)(r4)
849 ld r29, VCPU_GPR(R29)(r4)
850 ld r30, VCPU_GPR(R30)(r4)
851 ld r31, VCPU_GPR(R31)(r4)
853 /* Switch DSCR to guest value */
858 /* Skip next section on POWER7 */
860 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
861 /* Load up POWER8-specific registers */
863 lwz r6, VCPU_PSPB(r4)
869 ld r6, VCPU_DAWRX(r4)
870 ld r7, VCPU_CIABR(r4)
877 ld r8, VCPU_EBBHR(r4)
880 ld r5, VCPU_EBBRR(r4)
881 ld r6, VCPU_BESCR(r4)
882 lwz r7, VCPU_GUEST_PID(r4)
890 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
892 /* POWER8-only registers */
893 ld r5, VCPU_TCSCR(r4)
895 ld r7, VCPU_CSIGR(r4)
902 /* POWER9-only registers */
904 ld r6, VCPU_PSSCR(r4)
905 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
906 ld r7, VCPU_HFSCR(r4)
910 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
914 * Set the decrementer to the guest decrementer.
916 ld r8,VCPU_DEC_EXPIRES(r4)
917 /* r8 is a host timebase value here, convert to guest TB */
918 ld r5,HSTATE_KVM_VCORE(r13)
919 ld r6,VCORE_TB_OFFSET(r5)
926 ld r5, VCPU_SPRG0(r4)
927 ld r6, VCPU_SPRG1(r4)
928 ld r7, VCPU_SPRG2(r4)
929 ld r8, VCPU_SPRG3(r4)
935 /* Load up DAR and DSISR */
937 lwz r6, VCPU_DSISR(r4)
941 /* Restore AMR and UAMOR, set AMOR to all 1s */
949 /* Restore state of CTRL run bit; assume 1 on entry */
957 /* Secondary threads wait for primary to have done partition switch */
958 ld r5, HSTATE_KVM_VCORE(r13)
959 lbz r6, HSTATE_PTID(r13)
962 lbz r0, VCORE_IN_GUEST(r5)
966 20: lwz r3, VCORE_ENTRY_EXIT(r5)
969 lbz r0, VCORE_IN_GUEST(r5)
979 /* Check if HDEC expires soon */
982 cmpdi r3, 512 /* 1 microsecond */
985 #ifdef CONFIG_KVM_XICS
986 /* We are entering the guest on that thread, push VCPU to XIVE */
987 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
990 ld r11, VCPU_XIVE_SAVED_STATE(r4)
994 lwz r11, VCPU_XIVE_CAM_WORD(r4)
995 li r9, TM_QW1_OS + TM_WORD2
998 stw r9, VCPU_XIVE_PUSHED(r4)
1001 #endif /* CONFIG_KVM_XICS */
1003 deliver_guest_interrupt:
1010 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1012 ld r11, VCPU_MSR(r4)
1013 ld r6, VCPU_SRR0(r4)
1014 ld r7, VCPU_SRR1(r4)
1018 /* r11 = vcpu->arch.msr & ~MSR_HV */
1019 rldicl r11, r11, 63 - MSR_HV_LG, 1
1020 rotldi r11, r11, 1 + MSR_HV_LG
1021 ori r11, r11, MSR_ME
1023 /* Check if we can deliver an external or decrementer interrupt now */
1024 ld r0, VCPU_PENDING_EXC(r4)
1025 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1027 andi. r8, r11, MSR_EE
1029 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1030 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1034 li r0, BOOK3S_INTERRUPT_EXTERNAL
1038 /* On POWER9 check whether the guest has large decrementer enabled */
1039 andis. r8, r8, LPCR_LD@h
1041 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1044 li r0, BOOK3S_INTERRUPT_DECREMENTER
1047 12: mtspr SPRN_SRR0, r10
1049 mtspr SPRN_SRR1, r11
1051 bl kvmppc_msr_interrupt
1055 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1056 /* On POWER9, check for pending doorbell requests */
1057 lbz r0, VCPU_DBELL_REQ(r4)
1059 beq fast_guest_return
1060 ld r5, HSTATE_KVM_VCORE(r13)
1061 /* Set DPDES register so the CPU will take a doorbell interrupt */
1063 mtspr SPRN_DPDES, r0
1064 std r0, VCORE_DPDES(r5)
1065 /* Make sure other cpus see vcore->dpdes set before dbell req clear */
1067 /* Clear the pending doorbell request */
1069 stb r0, VCPU_DBELL_REQ(r4)
1074 * R10: value for HSRR0
1075 * R11: value for HSRR1
1080 stb r0,VCPU_CEDED(r4) /* cancel cede */
1081 mtspr SPRN_HSRR0,r10
1082 mtspr SPRN_HSRR1,r11
1084 /* Activate guest mode, so faults get handled by KVM */
1085 li r9, KVM_GUEST_MODE_GUEST_HV
1086 stb r9, HSTATE_IN_GUEST(r13)
1088 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1089 /* Accumulate timing */
1090 addi r3, r4, VCPU_TB_GUEST
1091 bl kvmhv_accumulate_time
1097 ld r5, VCPU_CFAR(r4)
1099 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1102 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1109 ld r1, VCPU_GPR(R1)(r4)
1110 ld r2, VCPU_GPR(R2)(r4)
1111 ld r3, VCPU_GPR(R3)(r4)
1112 ld r5, VCPU_GPR(R5)(r4)
1113 ld r6, VCPU_GPR(R6)(r4)
1114 ld r7, VCPU_GPR(R7)(r4)
1115 ld r8, VCPU_GPR(R8)(r4)
1116 ld r9, VCPU_GPR(R9)(r4)
1117 ld r10, VCPU_GPR(R10)(r4)
1118 ld r11, VCPU_GPR(R11)(r4)
1119 ld r12, VCPU_GPR(R12)(r4)
1120 ld r13, VCPU_GPR(R13)(r4)
1124 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1126 /* Move canary into DSISR to check for later */
1129 mtspr SPRN_HDSISR, r0
1130 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1132 ld r0, VCPU_GPR(R0)(r4)
1133 ld r4, VCPU_GPR(R4)(r4)
1142 stw r12, VCPU_TRAP(r4)
1143 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1144 addi r3, r4, VCPU_TB_RMEXIT
1145 bl kvmhv_accumulate_time
1147 11: b kvmhv_switch_to_host
1154 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1155 12: stw r12, VCPU_TRAP(r4)
1157 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1158 addi r3, r4, VCPU_TB_RMEXIT
1159 bl kvmhv_accumulate_time
1163 /******************************************************************************
1167 *****************************************************************************/
1170 * We come here from the first-level interrupt handlers.
1172 .globl kvmppc_interrupt_hv
1173 kvmppc_interrupt_hv:
1175 * Register contents:
1176 * R12 = (guest CR << 32) | interrupt vector
1178 * guest R12 saved in shadow VCPU SCRATCH0
1179 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1180 * guest R13 saved in SPRN_SCRATCH0
1182 std r9, HSTATE_SCRATCH2(r13)
1183 lbz r9, HSTATE_IN_GUEST(r13)
1184 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1185 beq kvmppc_bad_host_intr
1186 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1187 cmpwi r9, KVM_GUEST_MODE_GUEST
1188 ld r9, HSTATE_SCRATCH2(r13)
1189 beq kvmppc_interrupt_pr
1191 /* We're now back in the host but in guest MMU context */
1192 li r9, KVM_GUEST_MODE_HOST_HV
1193 stb r9, HSTATE_IN_GUEST(r13)
1195 ld r9, HSTATE_KVM_VCPU(r13)
1197 /* Save registers */
1199 std r0, VCPU_GPR(R0)(r9)
1200 std r1, VCPU_GPR(R1)(r9)
1201 std r2, VCPU_GPR(R2)(r9)
1202 std r3, VCPU_GPR(R3)(r9)
1203 std r4, VCPU_GPR(R4)(r9)
1204 std r5, VCPU_GPR(R5)(r9)
1205 std r6, VCPU_GPR(R6)(r9)
1206 std r7, VCPU_GPR(R7)(r9)
1207 std r8, VCPU_GPR(R8)(r9)
1208 ld r0, HSTATE_SCRATCH2(r13)
1209 std r0, VCPU_GPR(R9)(r9)
1210 std r10, VCPU_GPR(R10)(r9)
1211 std r11, VCPU_GPR(R11)(r9)
1212 ld r3, HSTATE_SCRATCH0(r13)
1213 std r3, VCPU_GPR(R12)(r9)
1214 /* CR is in the high half of r12 */
1218 ld r3, HSTATE_CFAR(r13)
1219 std r3, VCPU_CFAR(r9)
1220 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1222 ld r4, HSTATE_PPR(r13)
1223 std r4, VCPU_PPR(r9)
1224 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1226 /* Restore R1/R2 so we can handle faults */
1227 ld r1, HSTATE_HOST_R1(r13)
1230 mfspr r10, SPRN_SRR0
1231 mfspr r11, SPRN_SRR1
1232 std r10, VCPU_SRR0(r9)
1233 std r11, VCPU_SRR1(r9)
1234 /* trap is in the low half of r12, clear CR from the high half */
1236 andi. r0, r12, 2 /* need to read HSRR0/1? */
1238 mfspr r10, SPRN_HSRR0
1239 mfspr r11, SPRN_HSRR1
1241 1: std r10, VCPU_PC(r9)
1242 std r11, VCPU_MSR(r9)
1246 std r3, VCPU_GPR(R13)(r9)
1249 stw r12,VCPU_TRAP(r9)
1252 * Now that we have saved away SRR0/1 and HSRR0/1,
1253 * interrupts are recoverable in principle, so set MSR_RI.
1254 * This becomes important for relocation-on interrupts from
1255 * the guest, which we can get in radix mode on POWER9.
1260 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1261 addi r3, r9, VCPU_TB_RMINTR
1263 bl kvmhv_accumulate_time
1264 ld r5, VCPU_GPR(R5)(r9)
1265 ld r6, VCPU_GPR(R6)(r9)
1266 ld r7, VCPU_GPR(R7)(r9)
1267 ld r8, VCPU_GPR(R8)(r9)
1270 /* Save HEIR (HV emulation assist reg) in emul_inst
1271 if this is an HEI (HV emulation interrupt, e40) */
1272 li r3,KVM_INST_FETCH_FAILED
1273 stw r3,VCPU_LAST_INST(r9)
1274 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1277 11: stw r3,VCPU_HEIR(r9)
1279 /* these are volatile across C function calls */
1280 #ifdef CONFIG_RELOCATABLE
1281 ld r3, HSTATE_SCRATCH1(r13)
1287 std r3, VCPU_CTR(r9)
1288 std r4, VCPU_XER(r9)
1290 /* If this is a page table miss then see if it's theirs or ours */
1291 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1293 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1296 /* See if this is a leftover HDEC interrupt */
1297 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1303 bge fast_guest_return
1305 /* See if this is an hcall we can handle in real mode */
1306 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1307 beq hcall_try_real_mode
1309 /* Hypervisor doorbell - exit only if host IPI flag set */
1310 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1315 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1316 lbz r0, HSTATE_HOST_IPI(r13)
1321 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1322 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1324 mfspr r3, SPRN_HFSCR
1325 std r3, VCPU_HFSCR(r9)
1328 /* External interrupt ? */
1329 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1330 bne+ guest_exit_cont
1332 /* External interrupt, first check for host_ipi. If this is
1333 * set, we know the host wants us out so let's do it now
1338 * Restore the active volatile registers after returning from
1341 ld r9, HSTATE_KVM_VCPU(r13)
1342 li r12, BOOK3S_INTERRUPT_EXTERNAL
1345 * kvmppc_read_intr return codes:
1347 * Exit to host (r3 > 0)
1348 * 1 An interrupt is pending that needs to be handled by the host
1349 * Exit guest and return to host by branching to guest_exit_cont
1351 * 2 Passthrough that needs completion in the host
1352 * Exit guest and return to host by branching to guest_exit_cont
1353 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1354 * to indicate to the host to complete handling the interrupt
1356 * Before returning to guest, we check if any CPU is heading out
1357 * to the host and if so, we head out also. If no CPUs are heading
1358 * check return values <= 0.
1360 * Return to guest (r3 <= 0)
1361 * 0 No external interrupt is pending
1362 * -1 A guest wakeup IPI (which has now been cleared)
1363 * In either case, we return to guest to deliver any pending
1366 * -2 A PCI passthrough external interrupt was handled
1367 * (interrupt was delivered directly to guest)
1368 * Return to guest to deliver any pending guest interrupts.
1374 /* Return code = 2 */
1375 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1376 stw r12, VCPU_TRAP(r9)
1379 1: /* Return code <= 1 */
1383 /* Return code <= 0 */
1384 4: ld r5, HSTATE_KVM_VCORE(r13)
1385 lwz r0, VCORE_ENTRY_EXIT(r5)
1388 blt deliver_guest_interrupt
1390 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1391 #ifdef CONFIG_KVM_XICS
1392 /* We are exiting, pull the VP from the XIVE */
1393 lwz r0, VCPU_XIVE_PUSHED(r9)
1396 li r7, TM_SPC_PULL_OS_CTX
1399 andi. r0, r0, MSR_IR /* in real mode? */
1401 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1404 /* First load to pull the context, we ignore the value */
1407 /* Second load to recover the context state (Words 0 and 1) */
1410 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1413 /* First load to pull the context, we ignore the value */
1416 /* Second load to recover the context state (Words 0 and 1) */
1418 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1419 /* Fixup some of the state for the next load */
1422 stw r10, VCPU_XIVE_PUSHED(r9)
1423 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1424 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1427 #endif /* CONFIG_KVM_XICS */
1428 /* Save more register state */
1431 std r6, VCPU_DAR(r9)
1432 stw r7, VCPU_DSISR(r9)
1433 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1434 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1436 std r6, VCPU_FAULT_DAR(r9)
1437 stw r7, VCPU_FAULT_DSISR(r9)
1439 /* See if it is a machine check */
1440 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1441 beq machine_check_realmode
1443 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1444 addi r3, r9, VCPU_TB_RMEXIT
1446 bl kvmhv_accumulate_time
1450 /* Increment exit count, poke other threads to exit */
1451 bl kvmhv_commence_exit
1453 ld r9, HSTATE_KVM_VCPU(r13)
1454 lwz r12, VCPU_TRAP(r9)
1456 /* Stop others sending VCPU interrupts to this physical CPU */
1458 stw r0, VCPU_CPU(r9)
1459 stw r0, VCPU_THREAD_CPU(r9)
1461 /* Save guest CTRL register, set runlatch to 1 */
1463 stw r6,VCPU_CTRL(r9)
1469 /* Check if we are running hash or radix and store it in cr2 */
1471 lbz r0, KVM_RADIX(r5)
1474 /* Read the guest SLB and save it away */
1476 bne cr2, 3f /* for radix, save 0 entries */
1477 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1482 andis. r0,r8,SLB_ESID_V@h
1484 add r8,r8,r6 /* put index in */
1486 std r8,VCPU_SLB_E(r7)
1487 std r3,VCPU_SLB_V(r7)
1488 addi r7,r7,VCPU_SLB_SIZE
1492 3: stw r5,VCPU_SLB_MAX(r9)
1495 * Save the guest PURR/SPURR
1500 ld r8,VCPU_SPURR(r9)
1501 std r5,VCPU_PURR(r9)
1502 std r6,VCPU_SPURR(r9)
1507 * Restore host PURR/SPURR and add guest times
1508 * so that the time in the guest gets accounted.
1510 ld r3,HSTATE_PURR(r13)
1511 ld r4,HSTATE_SPURR(r13)
1518 ld r3, HSTATE_KVM_VCORE(r13)
1521 /* On P9, if the guest has large decr enabled, don't sign extend */
1523 ld r4, VCORE_LPCR(r3)
1524 andis. r4, r4, LPCR_LD@h
1526 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1529 /* r5 is a guest timebase value here, convert to host TB */
1530 ld r4,VCORE_TB_OFFSET(r3)
1532 std r5,VCPU_DEC_EXPIRES(r9)
1536 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1537 /* Save POWER8-specific registers */
1541 std r5, VCPU_IAMR(r9)
1542 stw r6, VCPU_PSPB(r9)
1543 std r7, VCPU_FSCR(r9)
1547 std r7, VCPU_TAR(r9)
1548 mfspr r8, SPRN_EBBHR
1549 std r8, VCPU_EBBHR(r9)
1550 mfspr r5, SPRN_EBBRR
1551 mfspr r6, SPRN_BESCR
1554 std r5, VCPU_EBBRR(r9)
1555 std r6, VCPU_BESCR(r9)
1556 stw r7, VCPU_GUEST_PID(r9)
1557 std r8, VCPU_WORT(r9)
1559 mfspr r5, SPRN_TCSCR
1561 mfspr r7, SPRN_CSIGR
1563 std r5, VCPU_TCSCR(r9)
1564 std r6, VCPU_ACOP(r9)
1565 std r7, VCPU_CSIGR(r9)
1566 std r8, VCPU_TACR(r9)
1569 mfspr r6, SPRN_PSSCR
1570 std r5, VCPU_TID(r9)
1571 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1573 std r6, VCPU_PSSCR(r9)
1574 /* Restore host HFSCR value */
1575 ld r7, STACK_SLOT_HFSCR(r1)
1576 mtspr SPRN_HFSCR, r7
1577 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1579 * Restore various registers to 0, where non-zero values
1580 * set by the guest could disrupt the host.
1587 mtspr SPRN_TCSCR, r0
1588 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1591 mtspr SPRN_MMCRS, r0
1592 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1595 /* Save and reset AMR and UAMOR before turning on the MMU */
1599 std r6,VCPU_UAMOR(r9)
1602 mtspr SPRN_UAMOR, r6
1604 /* Switch DSCR back to host value */
1606 ld r7, HSTATE_DSCR(r13)
1607 std r8, VCPU_DSCR(r9)
1610 /* Save non-volatile GPRs */
1611 std r14, VCPU_GPR(R14)(r9)
1612 std r15, VCPU_GPR(R15)(r9)
1613 std r16, VCPU_GPR(R16)(r9)
1614 std r17, VCPU_GPR(R17)(r9)
1615 std r18, VCPU_GPR(R18)(r9)
1616 std r19, VCPU_GPR(R19)(r9)
1617 std r20, VCPU_GPR(R20)(r9)
1618 std r21, VCPU_GPR(R21)(r9)
1619 std r22, VCPU_GPR(R22)(r9)
1620 std r23, VCPU_GPR(R23)(r9)
1621 std r24, VCPU_GPR(R24)(r9)
1622 std r25, VCPU_GPR(R25)(r9)
1623 std r26, VCPU_GPR(R26)(r9)
1624 std r27, VCPU_GPR(R27)(r9)
1625 std r28, VCPU_GPR(R28)(r9)
1626 std r29, VCPU_GPR(R29)(r9)
1627 std r30, VCPU_GPR(R30)(r9)
1628 std r31, VCPU_GPR(R31)(r9)
1631 mfspr r3, SPRN_SPRG0
1632 mfspr r4, SPRN_SPRG1
1633 mfspr r5, SPRN_SPRG2
1634 mfspr r6, SPRN_SPRG3
1635 std r3, VCPU_SPRG0(r9)
1636 std r4, VCPU_SPRG1(r9)
1637 std r5, VCPU_SPRG2(r9)
1638 std r6, VCPU_SPRG3(r9)
1644 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1647 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
1650 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1653 /* Increment yield count if they have a VPA */
1654 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1657 li r4, LPPACA_YIELDCOUNT
1662 stb r3, VCPU_VPA_DIRTY(r9)
1664 /* Save PMU registers if requested */
1665 /* r8 and cr0.eq are live here */
1668 * POWER8 seems to have a hardware bug where setting
1669 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1670 * when some counters are already negative doesn't seem
1671 * to cause a performance monitor alert (and hence interrupt).
1672 * The effect of this is that when saving the PMU state,
1673 * if there is no PMU alert pending when we read MMCR0
1674 * before freezing the counters, but one becomes pending
1675 * before we read the counters, we lose it.
1676 * To work around this, we need a way to freeze the counters
1677 * before reading MMCR0. Normally, freezing the counters
1678 * is done by writing MMCR0 (to set MMCR0[FC]) which
1679 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1680 * we can also freeze the counters using MMCR2, by writing
1681 * 1s to all the counter freeze condition bits (there are
1682 * 9 bits each for 6 counters).
1684 li r3, -1 /* set all freeze bits */
1686 mfspr r10, SPRN_MMCR2
1687 mtspr SPRN_MMCR2, r3
1689 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1691 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1692 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1693 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1694 mfspr r6, SPRN_MMCRA
1695 /* Clear MMCRA in order to disable SDAR updates */
1697 mtspr SPRN_MMCRA, r7
1699 beq 21f /* if no VPA, save PMU stuff anyway */
1700 lbz r7, LPPACA_PMCINUSE(r8)
1701 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1703 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1705 21: mfspr r5, SPRN_MMCR1
1708 std r4, VCPU_MMCR(r9)
1709 std r5, VCPU_MMCR + 8(r9)
1710 std r6, VCPU_MMCR + 16(r9)
1712 std r10, VCPU_MMCR + 24(r9)
1713 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1714 std r7, VCPU_SIAR(r9)
1715 std r8, VCPU_SDAR(r9)
1722 stw r3, VCPU_PMC(r9)
1723 stw r4, VCPU_PMC + 4(r9)
1724 stw r5, VCPU_PMC + 8(r9)
1725 stw r6, VCPU_PMC + 12(r9)
1726 stw r7, VCPU_PMC + 16(r9)
1727 stw r8, VCPU_PMC + 20(r9)
1730 std r5, VCPU_SIER(r9)
1731 BEGIN_FTR_SECTION_NESTED(96)
1732 mfspr r6, SPRN_SPMC1
1733 mfspr r7, SPRN_SPMC2
1734 mfspr r8, SPRN_MMCRS
1735 stw r6, VCPU_PMC + 24(r9)
1736 stw r7, VCPU_PMC + 28(r9)
1737 std r8, VCPU_MMCR + 32(r9)
1739 mtspr SPRN_MMCRS, r4
1740 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1741 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1744 /* Restore host values of some registers */
1746 ld r5, STACK_SLOT_CIABR(r1)
1747 ld r6, STACK_SLOT_DAWR(r1)
1748 ld r7, STACK_SLOT_DAWRX(r1)
1749 mtspr SPRN_CIABR, r5
1751 mtspr SPRN_DAWRX, r7
1752 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1754 ld r5, STACK_SLOT_TID(r1)
1755 ld r6, STACK_SLOT_PSSCR(r1)
1756 ld r7, STACK_SLOT_PID(r1)
1757 ld r8, STACK_SLOT_IAMR(r1)
1759 mtspr SPRN_PSSCR, r6
1762 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1764 #ifdef CONFIG_PPC_RADIX_MMU
1766 * Are we running hash or radix ?
1769 lbz r0, KVM_RADIX(r5)
1773 /* Radix: Handle the case where the guest used an illegal PID */
1774 LOAD_REG_ADDR(r4, mmu_base_pid)
1775 lwz r3, VCPU_GUEST_PID(r9)
1781 * Illegal PID, the HW might have prefetched and cached in the TLB
1782 * some translations for the LPID 0 / guest PID combination which
1783 * Linux doesn't know about, so we need to flush that PID out of
1784 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1785 * the right context.
1791 /* Then do a congruence class local flush */
1793 lwz r0,KVM_TLB_SETS(r6)
1795 li r7,0x400 /* IS field = 0b01 */
1797 sldi r0,r3,32 /* RS has PID */
1798 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1803 2: /* Flush the ERAT on radix P9 DD1 guest exit */
1806 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1808 #endif /* CONFIG_PPC_RADIX_MMU */
1810 /* Hash: clear out SLB */
1817 * POWER7/POWER8 guest -> host partition switch code.
1818 * We don't have to lock against tlbies but we do
1819 * have to coordinate the hardware threads.
1821 kvmhv_switch_to_host:
1822 /* Secondary threads wait for primary to do partition switch */
1823 ld r5,HSTATE_KVM_VCORE(r13)
1824 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1825 lbz r3,HSTATE_PTID(r13)
1829 13: lbz r3,VCORE_IN_GUEST(r5)
1835 /* Primary thread waits for all the secondaries to exit guest */
1836 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1837 rlwinm r0,r3,32-8,0xff
1843 /* Did we actually switch to the guest at all? */
1844 lbz r6, VCORE_IN_GUEST(r5)
1848 /* Primary thread switches back to host partition */
1849 lwz r7,KVM_HOST_LPID(r4)
1851 ld r6,KVM_HOST_SDR1(r4)
1852 li r8,LPID_RSVD /* switch to reserved LPID */
1855 mtspr SPRN_SDR1,r6 /* switch to host page table */
1856 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1861 /* DPDES and VTB are shared between threads */
1862 mfspr r7, SPRN_DPDES
1864 std r7, VCORE_DPDES(r5)
1865 std r8, VCORE_VTB(r5)
1866 /* clear DPDES so we don't get guest doorbells in the host */
1868 mtspr SPRN_DPDES, r8
1869 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1871 /* If HMI, call kvmppc_realmode_hmi_handler() */
1872 cmpwi r12, BOOK3S_INTERRUPT_HMI
1874 bl kvmppc_realmode_hmi_handler
1876 li r12, BOOK3S_INTERRUPT_HMI
1878 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1879 * the TB. Hence it is not required to subtract guest timebase
1880 * offset from timebase. So, skip it.
1882 * Also, do not call kvmppc_subcore_exit_guest() because it has
1883 * been invoked as part of kvmppc_realmode_hmi_handler().
1888 /* Subtract timebase offset from timebase */
1889 ld r8,VCORE_TB_OFFSET(r5)
1892 mftb r6 /* current guest timebase */
1894 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1895 mftb r7 /* check if lower 24 bits overflowed */
1900 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1903 17: bl kvmppc_subcore_exit_guest
1905 30: ld r5,HSTATE_KVM_VCORE(r13)
1906 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1909 ld r0, VCORE_PCR(r5)
1915 /* Signal secondary CPUs to continue */
1916 stb r0,VCORE_IN_GUEST(r5)
1917 19: lis r8,0x7fff /* MAX_INT@h */
1920 16: ld r8,KVM_HOST_LPCR(r4)
1924 /* load host SLB entries */
1925 BEGIN_MMU_FTR_SECTION
1927 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1928 ld r8,PACA_SLBSHADOWPTR(r13)
1930 .rept SLB_NUM_BOLTED
1931 li r3, SLBSHADOW_SAVEAREA
1935 andis. r7,r5,SLB_ESID_V@h
1941 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1942 /* Finish timing, if we have a vcpu */
1943 ld r4, HSTATE_KVM_VCPU(r13)
1947 bl kvmhv_accumulate_time
1950 /* Unset guest mode */
1951 li r0, KVM_GUEST_MODE_NONE
1952 stb r0, HSTATE_IN_GUEST(r13)
1954 ld r0, SFS+PPC_LR_STKOFF(r1)
1960 * Check whether an HDSI is an HPTE not found fault or something else.
1961 * If it is an HPTE not found fault that is due to the guest accessing
1962 * a page that they have mapped but which we have paged out, then
1963 * we continue on with the guest exit path. In all other cases,
1964 * reflect the HDSI to the guest as a DSI.
1968 lbz r0, KVM_RADIX(r3)
1970 mfspr r6, SPRN_HDSISR
1972 /* Look for DSISR canary. If we find it, retry instruction */
1975 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1977 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
1978 /* HPTE not found fault or protection fault? */
1979 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1980 beq 1f /* if not, send it to the guest */
1981 andi. r0, r11, MSR_DR /* data relocation enabled? */
1984 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1986 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1988 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1989 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1990 bne 7f /* if no SLB entry found */
1991 4: std r4, VCPU_FAULT_DAR(r9)
1992 stw r6, VCPU_FAULT_DSISR(r9)
1994 /* Search the hash table. */
1995 mr r3, r9 /* vcpu pointer */
1996 li r7, 1 /* data fault */
1997 bl kvmppc_hpte_hv_fault
1998 ld r9, HSTATE_KVM_VCPU(r13)
2000 ld r11, VCPU_MSR(r9)
2001 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2002 cmpdi r3, 0 /* retry the instruction */
2004 cmpdi r3, -1 /* handle in kernel mode */
2006 cmpdi r3, -2 /* MMIO emulation; need instr word */
2009 /* Synthesize a DSI (or DSegI) for the guest */
2010 ld r4, VCPU_FAULT_DAR(r9)
2012 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2013 mtspr SPRN_DSISR, r6
2014 7: mtspr SPRN_DAR, r4
2015 mtspr SPRN_SRR0, r10
2016 mtspr SPRN_SRR1, r11
2018 bl kvmppc_msr_interrupt
2019 fast_interrupt_c_return:
2020 6: ld r7, VCPU_CTR(r9)
2027 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2028 ld r5, KVM_VRMA_SLB_V(r5)
2031 /* If this is for emulated MMIO, load the instruction word */
2032 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2034 /* Set guest mode to 'jump over instruction' so if lwz faults
2035 * we'll just continue at the next IP. */
2036 li r0, KVM_GUEST_MODE_SKIP
2037 stb r0, HSTATE_IN_GUEST(r13)
2039 /* Do the access with MSR:DR enabled */
2041 ori r4, r3, MSR_DR /* Enable paging for data */
2046 /* Store the result */
2047 stw r8, VCPU_LAST_INST(r9)
2049 /* Unset guest mode. */
2050 li r0, KVM_GUEST_MODE_HOST_HV
2051 stb r0, HSTATE_IN_GUEST(r13)
2055 std r4, VCPU_FAULT_DAR(r9)
2056 stw r6, VCPU_FAULT_DSISR(r9)
2059 std r5, VCPU_FAULT_GPA(r9)
2063 * Similarly for an HISI, reflect it to the guest as an ISI unless
2064 * it is an HPTE not found fault for a page that we have paged out.
2068 lbz r0, KVM_RADIX(r3)
2070 bne .Lradix_hisi /* for radix, just save ASDR */
2071 andis. r0, r11, SRR1_ISI_NOPT@h
2073 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2076 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2078 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2080 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2081 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2082 bne 7f /* if no SLB entry found */
2084 /* Search the hash table. */
2085 mr r3, r9 /* vcpu pointer */
2088 li r7, 0 /* instruction fault */
2089 bl kvmppc_hpte_hv_fault
2090 ld r9, HSTATE_KVM_VCPU(r13)
2092 ld r11, VCPU_MSR(r9)
2093 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2094 cmpdi r3, 0 /* retry the instruction */
2095 beq fast_interrupt_c_return
2096 cmpdi r3, -1 /* handle in kernel mode */
2099 /* Synthesize an ISI (or ISegI) for the guest */
2101 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2102 7: mtspr SPRN_SRR0, r10
2103 mtspr SPRN_SRR1, r11
2105 bl kvmppc_msr_interrupt
2106 b fast_interrupt_c_return
2108 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2109 ld r5, KVM_VRMA_SLB_V(r6)
2113 * Try to handle an hcall in real mode.
2114 * Returns to the guest if we handle it, or continues on up to
2115 * the kernel if we can't (i.e. if we don't have a handler for
2116 * it, or if the handler returns H_TOO_HARD).
2118 * r5 - r8 contain hcall args,
2119 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2121 hcall_try_real_mode:
2122 ld r3,VCPU_GPR(R3)(r9)
2124 /* sc 1 from userspace - reflect to guest syscall */
2125 bne sc_1_fast_return
2127 cmpldi r3,hcall_real_table_end - hcall_real_table
2129 /* See if this hcall is enabled for in-kernel handling */
2131 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2132 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2134 ld r0, KVM_ENABLED_HCALLS(r4)
2135 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2139 /* Get pointer to handler, if any, and call it */
2140 LOAD_REG_ADDR(r4, hcall_real_table)
2146 mr r3,r9 /* get vcpu pointer */
2147 ld r4,VCPU_GPR(R4)(r9)
2150 beq hcall_real_fallback
2151 ld r4,HSTATE_KVM_VCPU(r13)
2152 std r3,VCPU_GPR(R3)(r4)
2160 li r10, BOOK3S_INTERRUPT_SYSCALL
2161 bl kvmppc_msr_interrupt
2165 /* We've attempted a real mode hcall, but it's punted it back
2166 * to userspace. We need to restore some clobbered volatiles
2167 * before resuming the pass-it-to-qemu path */
2168 hcall_real_fallback:
2169 li r12,BOOK3S_INTERRUPT_SYSCALL
2170 ld r9, HSTATE_KVM_VCPU(r13)
2174 .globl hcall_real_table
2176 .long 0 /* 0 - unused */
2177 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2178 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2179 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2180 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2181 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2182 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2183 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2184 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2185 .long 0 /* 0x24 - H_SET_SPRG0 */
2186 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2201 #ifdef CONFIG_KVM_XICS
2202 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2203 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2204 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2205 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2206 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2208 .long 0 /* 0x64 - H_EOI */
2209 .long 0 /* 0x68 - H_CPPR */
2210 .long 0 /* 0x6c - H_IPI */
2211 .long 0 /* 0x70 - H_IPOLL */
2212 .long 0 /* 0x74 - H_XIRR */
2240 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2241 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2257 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2261 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2262 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2263 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2375 #ifdef CONFIG_KVM_XICS
2376 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2378 .long 0 /* 0x2fc - H_XIRR_X*/
2380 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2381 .globl hcall_real_table_end
2382 hcall_real_table_end:
2384 _GLOBAL(kvmppc_h_set_xdabr)
2385 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2387 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2390 6: li r3, H_PARAMETER
2393 _GLOBAL(kvmppc_h_set_dabr)
2394 li r5, DABRX_USER | DABRX_KERNEL
2398 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2399 std r4,VCPU_DABR(r3)
2400 stw r5, VCPU_DABRX(r3)
2401 mtspr SPRN_DABRX, r5
2402 /* Work around P7 bug where DABR can get corrupted on mtspr */
2403 1: mtspr SPRN_DABR,r4
2411 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2412 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2413 rlwimi r5, r4, 2, DAWRX_WT
2415 std r4, VCPU_DAWR(r3)
2416 std r5, VCPU_DAWRX(r3)
2418 mtspr SPRN_DAWRX, r5
2422 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2424 std r11,VCPU_MSR(r3)
2426 stb r0,VCPU_CEDED(r3)
2427 sync /* order setting ceded vs. testing prodded */
2428 lbz r5,VCPU_PRODDED(r3)
2430 bne kvm_cede_prodded
2431 li r12,0 /* set trap to 0 to say hcall is handled */
2432 stw r12,VCPU_TRAP(r3)
2434 std r0,VCPU_GPR(R3)(r3)
2437 * Set our bit in the bitmask of napping threads unless all the
2438 * other threads are already napping, in which case we send this
2441 ld r5,HSTATE_KVM_VCORE(r13)
2442 lbz r6,HSTATE_PTID(r13)
2443 lwz r8,VCORE_ENTRY_EXIT(r5)
2447 addi r6,r5,VCORE_NAPPING_THREADS
2454 /* order napping_threads update vs testing entry_exit_map */
2457 stb r0,HSTATE_NAPPING(r13)
2458 lwz r7,VCORE_ENTRY_EXIT(r5)
2460 bge 33f /* another thread already exiting */
2463 * Although not specifically required by the architecture, POWER7
2464 * preserves the following registers in nap mode, even if an SMT mode
2465 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2466 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2468 /* Save non-volatile GPRs */
2469 std r14, VCPU_GPR(R14)(r3)
2470 std r15, VCPU_GPR(R15)(r3)
2471 std r16, VCPU_GPR(R16)(r3)
2472 std r17, VCPU_GPR(R17)(r3)
2473 std r18, VCPU_GPR(R18)(r3)
2474 std r19, VCPU_GPR(R19)(r3)
2475 std r20, VCPU_GPR(R20)(r3)
2476 std r21, VCPU_GPR(R21)(r3)
2477 std r22, VCPU_GPR(R22)(r3)
2478 std r23, VCPU_GPR(R23)(r3)
2479 std r24, VCPU_GPR(R24)(r3)
2480 std r25, VCPU_GPR(R25)(r3)
2481 std r26, VCPU_GPR(R26)(r3)
2482 std r27, VCPU_GPR(R27)(r3)
2483 std r28, VCPU_GPR(R28)(r3)
2484 std r29, VCPU_GPR(R29)(r3)
2485 std r30, VCPU_GPR(R30)(r3)
2486 std r31, VCPU_GPR(R31)(r3)
2491 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2494 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2496 ld r9, HSTATE_KVM_VCPU(r13)
2498 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2502 * Set DEC to the smaller of DEC and HDEC, so that we wake
2503 * no later than the end of our timeslice (HDEC interrupts
2504 * don't wake us from nap).
2510 /* On P9 check whether the guest has large decrementer mode enabled */
2511 ld r6, HSTATE_KVM_VCORE(r13)
2512 ld r6, VCORE_LPCR(r6)
2513 andis. r6, r6, LPCR_LD@h
2515 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2522 /* save expiry time of guest decrementer */
2524 ld r4, HSTATE_KVM_VCPU(r13)
2525 ld r5, HSTATE_KVM_VCORE(r13)
2526 ld r6, VCORE_TB_OFFSET(r5)
2527 subf r3, r6, r3 /* convert to host TB value */
2528 std r3, VCPU_DEC_EXPIRES(r4)
2530 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2531 ld r4, HSTATE_KVM_VCPU(r13)
2532 addi r3, r4, VCPU_TB_CEDE
2533 bl kvmhv_accumulate_time
2536 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2539 * Take a nap until a decrementer or external or doobell interrupt
2540 * occurs, with PECE1 and PECE0 set in LPCR.
2541 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2542 * Also clear the runlatch bit before napping.
2545 mfspr r0, SPRN_CTRLF
2547 mtspr SPRN_CTRLT, r0
2551 stb r0,HSTATE_HWTHREAD_REQ(r13)
2552 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
2554 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2556 ori r5, r5, LPCR_PECEDH
2557 rlwimi r5, r3, 0, LPCR_PECEDP
2558 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2560 kvm_nap_sequence: /* desired LPCR value in r5 */
2563 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2564 * enable state loss = 1 (allow SMT mode switch)
2565 * requested level = 0 (just stop dispatching)
2567 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2568 mtspr SPRN_PSSCR, r3
2569 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2570 li r4, LPCR_PECE_HVEE@higher
2573 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2577 std r0, HSTATE_SCRATCH0(r13)
2579 ld r0, HSTATE_SCRATCH0(r13)
2586 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2595 /* get vcpu pointer */
2596 ld r4, HSTATE_KVM_VCPU(r13)
2598 /* Woken by external or decrementer interrupt */
2599 ld r1, HSTATE_HOST_R1(r13)
2601 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2602 addi r3, r4, VCPU_TB_RMINTR
2603 bl kvmhv_accumulate_time
2606 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2609 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2611 bl kvmppc_restore_tm
2612 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2615 /* load up FP state */
2618 /* Restore guest decrementer */
2619 ld r3, VCPU_DEC_EXPIRES(r4)
2620 ld r5, HSTATE_KVM_VCORE(r13)
2621 ld r6, VCORE_TB_OFFSET(r5)
2622 add r3, r3, r6 /* convert host TB to guest TB value */
2628 ld r14, VCPU_GPR(R14)(r4)
2629 ld r15, VCPU_GPR(R15)(r4)
2630 ld r16, VCPU_GPR(R16)(r4)
2631 ld r17, VCPU_GPR(R17)(r4)
2632 ld r18, VCPU_GPR(R18)(r4)
2633 ld r19, VCPU_GPR(R19)(r4)
2634 ld r20, VCPU_GPR(R20)(r4)
2635 ld r21, VCPU_GPR(R21)(r4)
2636 ld r22, VCPU_GPR(R22)(r4)
2637 ld r23, VCPU_GPR(R23)(r4)
2638 ld r24, VCPU_GPR(R24)(r4)
2639 ld r25, VCPU_GPR(R25)(r4)
2640 ld r26, VCPU_GPR(R26)(r4)
2641 ld r27, VCPU_GPR(R27)(r4)
2642 ld r28, VCPU_GPR(R28)(r4)
2643 ld r29, VCPU_GPR(R29)(r4)
2644 ld r30, VCPU_GPR(R30)(r4)
2645 ld r31, VCPU_GPR(R31)(r4)
2647 /* Check the wake reason in SRR1 to see why we got here */
2648 bl kvmppc_check_wake_reason
2651 * Restore volatile registers since we could have called a
2652 * C routine in kvmppc_check_wake_reason
2654 * r3 tells us whether we need to return to host or not
2655 * WARNING: it gets checked further down:
2656 * should not modify r3 until this check is done.
2658 ld r4, HSTATE_KVM_VCPU(r13)
2660 /* clear our bit in vcore->napping_threads */
2661 34: ld r5,HSTATE_KVM_VCORE(r13)
2662 lbz r7,HSTATE_PTID(r13)
2665 addi r6,r5,VCORE_NAPPING_THREADS
2671 stb r0,HSTATE_NAPPING(r13)
2673 /* See if the wake reason saved in r3 means we need to exit */
2674 stw r12, VCPU_TRAP(r4)
2679 /* see if any other thread is already exiting */
2680 lwz r0,VCORE_ENTRY_EXIT(r5)
2684 b kvmppc_cede_reentry /* if not go back to guest */
2686 /* cede when already previously prodded case */
2689 stb r0,VCPU_PRODDED(r3)
2690 sync /* order testing prodded vs. clearing ceded */
2691 stb r0,VCPU_CEDED(r3)
2695 /* we've ceded but we want to give control to the host */
2697 ld r9, HSTATE_KVM_VCPU(r13)
2700 /* Try to handle a machine check in real mode */
2701 machine_check_realmode:
2702 mr r3, r9 /* get vcpu pointer */
2703 bl kvmppc_realmode_machine_check
2705 ld r9, HSTATE_KVM_VCPU(r13)
2706 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2708 * For the guest that is FWNMI capable, deliver all the MCE errors
2709 * (handled/unhandled) by exiting the guest with KVM_EXIT_NMI exit
2710 * reason. This new approach injects machine check errors in guest
2711 * address space to guest with additional information in the form
2712 * of RTAS event, thus enabling guest kernel to suitably handle
2715 * For the guest that is not FWNMI capable (old QEMU) fallback
2716 * to old behaviour for backward compatibility:
2717 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest either
2718 * through machine check interrupt (set HSRR0 to 0x200).
2719 * For handled errors (no-fatal), just go back to guest execution
2720 * with current HSRR0.
2721 * if we receive machine check with MSR(RI=0) then deliver it to
2722 * guest as machine check causing guest to crash.
2724 ld r11, VCPU_MSR(r9)
2725 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2726 bne mc_cont /* if so, exit to host */
2727 /* Check if guest is capable of handling NMI exit */
2728 ld r10, VCPU_KVM(r9)
2729 lbz r10, KVM_FWNMI(r10)
2730 cmpdi r10, 1 /* FWNMI capable? */
2731 beq mc_cont /* if so, exit with KVM_EXIT_NMI. */
2733 /* if not, fall through for backward compatibility. */
2734 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2735 beq 1f /* Deliver a machine check to guest */
2737 cmpdi r3, 0 /* Did we handle MCE ? */
2738 bne 2f /* Continue guest execution. */
2739 /* If not, deliver a machine check. SRR0/1 are already set */
2740 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2741 bl kvmppc_msr_interrupt
2742 2: b fast_interrupt_c_return
2745 * Check the reason we woke from nap, and take appropriate action.
2747 * 0 if nothing needs to be done
2748 * 1 if something happened that needs to be handled by the host
2749 * -1 if there was a guest wakeup (IPI or msgsnd)
2750 * -2 if we handled a PCI passthrough interrupt (returned by
2751 * kvmppc_read_intr only)
2753 * Also sets r12 to the interrupt vector for any interrupt that needs
2754 * to be handled now by the host (0x500 for external interrupt), or zero.
2755 * Modifies all volatile registers (since it may call a C function).
2756 * This routine calls kvmppc_read_intr, a C function, if an external
2757 * interrupt is pending.
2759 kvmppc_check_wake_reason:
2762 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2764 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2765 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2766 cmpwi r6, 8 /* was it an external interrupt? */
2767 beq 7f /* if so, see what it was */
2770 cmpwi r6, 6 /* was it the decrementer? */
2773 cmpwi r6, 5 /* privileged doorbell? */
2775 cmpwi r6, 3 /* hypervisor doorbell? */
2777 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2778 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2780 li r3, 1 /* anything else, return 1 */
2783 /* hypervisor doorbell */
2784 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2787 * Clear the doorbell as we will invoke the handler
2788 * explicitly in the guest exit path.
2790 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2792 /* see if it's a host IPI */
2797 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2798 lbz r0, HSTATE_HOST_IPI(r13)
2801 /* if not, return -1 */
2805 /* Woken up due to Hypervisor maintenance interrupt */
2806 4: li r12, BOOK3S_INTERRUPT_HMI
2810 /* external interrupt - create a stack frame so we can call C */
2812 std r0, PPC_LR_STKOFF(r1)
2813 stdu r1, -PPC_MIN_STKFRM(r1)
2816 li r12, BOOK3S_INTERRUPT_EXTERNAL
2821 * Return code of 2 means PCI passthrough interrupt, but
2822 * we need to return back to host to complete handling the
2823 * interrupt. Trap reason is expected in r12 by guest
2826 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2828 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2829 addi r1, r1, PPC_MIN_STKFRM
2834 * Save away FP, VMX and VSX registers.
2836 * N.B. r30 and r31 are volatile across this function,
2837 * thus it is not callable from C.
2844 #ifdef CONFIG_ALTIVEC
2846 oris r8,r8,MSR_VEC@h
2847 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2851 oris r8,r8,MSR_VSX@h
2852 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2855 addi r3,r3,VCPU_FPRS
2857 #ifdef CONFIG_ALTIVEC
2859 addi r3,r31,VCPU_VRS
2861 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2863 mfspr r6,SPRN_VRSAVE
2864 stw r6,VCPU_VRSAVE(r31)
2869 * Load up FP, VMX and VSX registers
2871 * N.B. r30 and r31 are volatile across this function,
2872 * thus it is not callable from C.
2879 #ifdef CONFIG_ALTIVEC
2881 oris r8,r8,MSR_VEC@h
2882 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2886 oris r8,r8,MSR_VSX@h
2887 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2890 addi r3,r4,VCPU_FPRS
2892 #ifdef CONFIG_ALTIVEC
2894 addi r3,r31,VCPU_VRS
2896 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2898 lwz r7,VCPU_VRSAVE(r31)
2899 mtspr SPRN_VRSAVE,r7
2904 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2906 * Save transactional state and TM-related registers.
2907 * Called with r9 pointing to the vcpu struct.
2908 * This can modify all checkpointed registers, but
2909 * restores r1, r2 and r9 (vcpu pointer) before exit.
2913 std r0, PPC_LR_STKOFF(r1)
2918 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2922 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2923 beq 1f /* TM not active in guest. */
2925 std r1, HSTATE_HOST_R1(r13)
2926 li r3, TM_CAUSE_KVM_RESCHED
2928 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2932 /* All GPRs are volatile at this point. */
2935 /* Temporarily store r13 and r9 so we have some regs to play with */
2938 std r9, PACATMSCRATCH(r13)
2939 ld r9, HSTATE_KVM_VCPU(r13)
2941 /* Get a few more GPRs free. */
2942 std r29, VCPU_GPRS_TM(29)(r9)
2943 std r30, VCPU_GPRS_TM(30)(r9)
2944 std r31, VCPU_GPRS_TM(31)(r9)
2946 /* Save away PPR and DSCR soon so don't run with user values. */
2949 mfspr r30, SPRN_DSCR
2950 ld r29, HSTATE_DSCR(r13)
2951 mtspr SPRN_DSCR, r29
2953 /* Save all but r9, r13 & r29-r31 */
2956 .if (reg != 9) && (reg != 13)
2957 std reg, VCPU_GPRS_TM(reg)(r9)
2961 /* ... now save r13 */
2963 std r4, VCPU_GPRS_TM(13)(r9)
2964 /* ... and save r9 */
2965 ld r4, PACATMSCRATCH(r13)
2966 std r4, VCPU_GPRS_TM(9)(r9)
2968 /* Reload stack pointer and TOC. */
2969 ld r1, HSTATE_HOST_R1(r13)
2972 /* Set MSR RI now we have r1 and r13 back. */
2976 /* Save away checkpinted SPRs. */
2977 std r31, VCPU_PPR_TM(r9)
2978 std r30, VCPU_DSCR_TM(r9)
2985 std r5, VCPU_LR_TM(r9)
2986 stw r6, VCPU_CR_TM(r9)
2987 std r7, VCPU_CTR_TM(r9)
2988 std r8, VCPU_AMR_TM(r9)
2989 std r10, VCPU_TAR_TM(r9)
2990 std r11, VCPU_XER_TM(r9)
2992 /* Restore r12 as trap number. */
2993 lwz r12, VCPU_TRAP(r9)
2996 addi r3, r9, VCPU_FPRS_TM
2998 addi r3, r9, VCPU_VRS_TM
3000 mfspr r6, SPRN_VRSAVE
3001 stw r6, VCPU_VRSAVE_TM(r9)
3004 * We need to save these SPRs after the treclaim so that the software
3005 * error code is recorded correctly in the TEXASR. Also the user may
3006 * change these outside of a transaction, so they must always be
3009 mfspr r5, SPRN_TFHAR
3010 mfspr r6, SPRN_TFIAR
3011 mfspr r7, SPRN_TEXASR
3012 std r5, VCPU_TFHAR(r9)
3013 std r6, VCPU_TFIAR(r9)
3014 std r7, VCPU_TEXASR(r9)
3016 ld r0, PPC_LR_STKOFF(r1)
3021 * Restore transactional state and TM-related registers.
3022 * Called with r4 pointing to the vcpu struct.
3023 * This potentially modifies all checkpointed registers.
3024 * It restores r1, r2, r4 from the PACA.
3028 std r0, PPC_LR_STKOFF(r1)
3030 /* Turn on TM/FP/VSX/VMX so we can restore them. */
3036 oris r5, r5, (MSR_VEC | MSR_VSX)@h
3040 * The user may change these outside of a transaction, so they must
3041 * always be context switched.
3043 ld r5, VCPU_TFHAR(r4)
3044 ld r6, VCPU_TFIAR(r4)
3045 ld r7, VCPU_TEXASR(r4)
3046 mtspr SPRN_TFHAR, r5
3047 mtspr SPRN_TFIAR, r6
3048 mtspr SPRN_TEXASR, r7
3051 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3052 beqlr /* TM not active in guest */
3053 std r1, HSTATE_HOST_R1(r13)
3055 /* Make sure the failure summary is set, otherwise we'll program check
3056 * when we trechkpt. It's possible that this might have been not set
3057 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
3060 oris r7, r7, (TEXASR_FS)@h
3061 mtspr SPRN_TEXASR, r7
3064 * We need to load up the checkpointed state for the guest.
3065 * We need to do this early as it will blow away any GPRs, VSRs and
3070 addi r3, r31, VCPU_FPRS_TM
3072 addi r3, r31, VCPU_VRS_TM
3075 lwz r7, VCPU_VRSAVE_TM(r4)
3076 mtspr SPRN_VRSAVE, r7
3078 ld r5, VCPU_LR_TM(r4)
3079 lwz r6, VCPU_CR_TM(r4)
3080 ld r7, VCPU_CTR_TM(r4)
3081 ld r8, VCPU_AMR_TM(r4)
3082 ld r9, VCPU_TAR_TM(r4)
3083 ld r10, VCPU_XER_TM(r4)
3092 * Load up PPR and DSCR values but don't put them in the actual SPRs
3093 * till the last moment to avoid running with userspace PPR and DSCR for
3096 ld r29, VCPU_DSCR_TM(r4)
3097 ld r30, VCPU_PPR_TM(r4)
3099 std r2, PACATMSCRATCH(r13) /* Save TOC */
3101 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3105 /* Load GPRs r0-r28 */
3108 ld reg, VCPU_GPRS_TM(reg)(r31)
3112 mtspr SPRN_DSCR, r29
3115 /* Load final GPRs */
3116 ld 29, VCPU_GPRS_TM(29)(r31)
3117 ld 30, VCPU_GPRS_TM(30)(r31)
3118 ld 31, VCPU_GPRS_TM(31)(r31)
3120 /* TM checkpointed state is now setup. All GPRs are now volatile. */
3123 /* Now let's get back the state we need. */
3126 ld r29, HSTATE_DSCR(r13)
3127 mtspr SPRN_DSCR, r29
3128 ld r4, HSTATE_KVM_VCPU(r13)
3129 ld r1, HSTATE_HOST_R1(r13)
3130 ld r2, PACATMSCRATCH(r13)
3132 /* Set the MSR RI since we have our registers back. */
3136 ld r0, PPC_LR_STKOFF(r1)
3142 * We come here if we get any exception or interrupt while we are
3143 * executing host real mode code while in guest MMU context.
3144 * For now just spin, but we should do something better.
3146 kvmppc_bad_host_intr:
3150 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3151 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3152 * r11 has the guest MSR value (in/out)
3153 * r9 has a vcpu pointer (in)
3154 * r0 is used as a scratch register
3156 kvmppc_msr_interrupt:
3157 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3158 cmpwi r0, 2 /* Check if we are in transactional state.. */
3159 ld r11, VCPU_INTR_MSR(r9)
3161 /* ... if transactional, change to suspended */
3163 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3167 * This works around a hardware bug on POWER8E processors, where
3168 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3169 * performance monitor interrupt. Instead, when we need to have
3170 * an interrupt pending, we have to arrange for a counter to overflow.
3174 mtspr SPRN_MMCR2, r3
3175 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3176 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3177 mtspr SPRN_MMCR0, r3
3184 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3186 * Start timing an activity
3187 * r3 = pointer to time accumulation struct, r4 = vcpu
3190 ld r5, HSTATE_KVM_VCORE(r13)
3191 lbz r6, VCORE_IN_GUEST(r5)
3193 beq 5f /* if in guest, need to */
3194 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3197 std r3, VCPU_CUR_ACTIVITY(r4)
3198 std r5, VCPU_ACTIVITY_START(r4)
3202 * Accumulate time to one activity and start another.
3203 * r3 = pointer to new time accumulation struct, r4 = vcpu
3205 kvmhv_accumulate_time:
3206 ld r5, HSTATE_KVM_VCORE(r13)
3207 lbz r8, VCORE_IN_GUEST(r5)
3209 beq 4f /* if in guest, need to */
3210 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3211 4: ld r5, VCPU_CUR_ACTIVITY(r4)
3212 ld r6, VCPU_ACTIVITY_START(r4)
3213 std r3, VCPU_CUR_ACTIVITY(r4)
3216 std r7, VCPU_ACTIVITY_START(r4)
3220 ld r8, TAS_SEQCOUNT(r5)
3223 std r8, TAS_SEQCOUNT(r5)
3225 ld r7, TAS_TOTAL(r5)
3227 std r7, TAS_TOTAL(r5)
3233 3: std r3, TAS_MIN(r5)
3239 std r8, TAS_SEQCOUNT(r5)