1 /*----------------------------------------------------------------------------+
2 | This source code is dual-licensed. You may use it under the terms of
3 | the GNU General Public License version 2, or under the license below.
5 | This source code has been made available to you by IBM on an AS-IS
6 | basis. Anyone receiving this source is licensed under IBM
7 | copyrights to use it in any way he or she deems fit, including
8 | copying it, modifying it, compiling it, and redistributing it either
9 | with or without modifications. No license under IBM patents or
10 | patent applications is to be implied by the copyright license.
12 | Any user of this software should understand that IBM cannot provide
13 | technical support for this software and will not be responsible for
14 | any consequences resulting from the use of this software.
16 | Any person who transfers this source code or any derivative work
17 | must include the IBM copyright notice, this paragraph, and the
18 | preceding two paragraphs in the transferred software.
20 | COPYRIGHT I B M CORPORATION 1999
21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 +----------------------------------------------------------------------------*/
28 * Include SoC specific headers
30 #if defined(CONFIG_405CR)
31 #include <asm/ppc405cr.h>
34 #if defined(CONFIG_405EP)
35 #include <asm/ppc405ep.h>
38 #if defined(CONFIG_405EX)
39 #include <asm/ppc405ex.h>
42 #if defined(CONFIG_405EZ)
43 #include <asm/ppc405ez.h>
46 #if defined(CONFIG_405GP)
47 #include <asm/ppc405gp.h>
50 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
51 #include <asm/ppc440ep_gr.h>
54 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
55 #include <asm/ppc440epx_grx.h>
58 #if defined(CONFIG_440GP)
59 #include <asm/ppc440gp.h>
62 #if defined(CONFIG_440GX)
63 #include <asm/ppc440gx.h>
66 #if defined(CONFIG_440SP)
67 #include <asm/ppc440sp.h>
70 #if defined(CONFIG_440SPE)
71 #include <asm/ppc440spe.h>
74 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
75 #include <asm/ppc460ex_gt.h>
78 #if defined(CONFIG_460SX)
79 #include <asm/ppc460sx.h>
82 #if defined(CONFIG_APM821XX)
83 #include <asm/apm821xx.h>
87 * Common registers for all SoC's
90 #define PLB3A0_ACR 0x0077
91 #define PLB4A0_ACR 0x0081
92 #define PLB4A1_ACR 0x0089
94 /* CPR register declarations */
96 #define PLB4Ax_ACR_PPM_MASK 0xf0000000
97 #define PLB4Ax_ACR_PPM_FIXED 0x00000000
98 #define PLB4Ax_ACR_PPM_FAIR 0xd0000000
99 #define PLB4Ax_ACR_HBU_MASK 0x08000000
100 #define PLB4Ax_ACR_HBU_DISABLED 0x00000000
101 #define PLB4Ax_ACR_HBU_ENABLED 0x08000000
102 #define PLB4Ax_ACR_RDP_MASK 0x06000000
103 #define PLB4Ax_ACR_RDP_DISABLED 0x00000000
104 #define PLB4Ax_ACR_RDP_2DEEP 0x02000000
105 #define PLB4Ax_ACR_RDP_3DEEP 0x04000000
106 #define PLB4Ax_ACR_RDP_4DEEP 0x06000000
107 #define PLB4Ax_ACR_WRP_MASK 0x01000000
108 #define PLB4Ax_ACR_WRP_DISABLED 0x00000000
109 #define PLB4Ax_ACR_WRP_2DEEP 0x01000000
112 * External Bus Controller
114 /* Values for EBC0_CFGADDR register - indirect addressing of these regs */
115 #define PB0CR 0x00 /* periph bank 0 config reg */
116 #define PB1CR 0x01 /* periph bank 1 config reg */
117 #define PB2CR 0x02 /* periph bank 2 config reg */
118 #define PB3CR 0x03 /* periph bank 3 config reg */
119 #define PB4CR 0x04 /* periph bank 4 config reg */
120 #define PB5CR 0x05 /* periph bank 5 config reg */
121 #define PB6CR 0x06 /* periph bank 6 config reg */
122 #define PB7CR 0x07 /* periph bank 7 config reg */
123 #define PB0AP 0x10 /* periph bank 0 access parameters */
124 #define PB1AP 0x11 /* periph bank 1 access parameters */
125 #define PB2AP 0x12 /* periph bank 2 access parameters */
126 #define PB3AP 0x13 /* periph bank 3 access parameters */
127 #define PB4AP 0x14 /* periph bank 4 access parameters */
128 #define PB5AP 0x15 /* periph bank 5 access parameters */
129 #define PB6AP 0x16 /* periph bank 6 access parameters */
130 #define PB7AP 0x17 /* periph bank 7 access parameters */
131 #define PBEAR 0x20 /* periph bus error addr reg */
132 #define PBESR0 0x21 /* periph bus error status reg 0 */
133 #define PBESR1 0x22 /* periph bus error status reg 1 */
134 #define EBC0_CFG 0x23 /* external bus configuration reg */
137 * GPIO macro register defines
139 /* todo: merge with gpio.h header */
140 #define GPIO_BASE GPIO0_BASE
142 #define GPIO0_OR (GPIO0_BASE + 0x0)
143 #define GPIO0_TCR (GPIO0_BASE + 0x4)
144 #define GPIO0_OSRL (GPIO0_BASE + 0x8)
145 #define GPIO0_OSRH (GPIO0_BASE + 0xC)
146 #define GPIO0_TSRL (GPIO0_BASE + 0x10)
147 #define GPIO0_TSRH (GPIO0_BASE + 0x14)
148 #define GPIO0_ODR (GPIO0_BASE + 0x18)
149 #define GPIO0_IR (GPIO0_BASE + 0x1C)
150 #define GPIO0_RR1 (GPIO0_BASE + 0x20)
151 #define GPIO0_RR2 (GPIO0_BASE + 0x24)
152 #define GPIO0_RR3 (GPIO0_BASE + 0x28)
153 #define GPIO0_ISR1L (GPIO0_BASE + 0x30)
154 #define GPIO0_ISR1H (GPIO0_BASE + 0x34)
155 #define GPIO0_ISR2L (GPIO0_BASE + 0x38)
156 #define GPIO0_ISR2H (GPIO0_BASE + 0x3C)
157 #define GPIO0_ISR3L (GPIO0_BASE + 0x40)
158 #define GPIO0_ISR3H (GPIO0_BASE + 0x44)
160 #define GPIO1_OR (GPIO1_BASE + 0x0)
161 #define GPIO1_TCR (GPIO1_BASE + 0x4)
162 #define GPIO1_OSRL (GPIO1_BASE + 0x8)
163 #define GPIO1_OSRH (GPIO1_BASE + 0xC)
164 #define GPIO1_TSRL (GPIO1_BASE + 0x10)
165 #define GPIO1_TSRH (GPIO1_BASE + 0x14)
166 #define GPIO1_ODR (GPIO1_BASE + 0x18)
167 #define GPIO1_IR (GPIO1_BASE + 0x1C)
168 #define GPIO1_RR1 (GPIO1_BASE + 0x20)
169 #define GPIO1_RR2 (GPIO1_BASE + 0x24)
170 #define GPIO1_RR3 (GPIO1_BASE + 0x28)
171 #define GPIO1_ISR1L (GPIO1_BASE + 0x30)
172 #define GPIO1_ISR1H (GPIO1_BASE + 0x34)
173 #define GPIO1_ISR2L (GPIO1_BASE + 0x38)
174 #define GPIO1_ISR2H (GPIO1_BASE + 0x3C)
175 #define GPIO1_ISR3L (GPIO1_BASE + 0x40)
176 #define GPIO1_ISR3H (GPIO1_BASE + 0x44)
178 /* General Purpose Timer (GPT) Register Offsets */
179 #define GPT0_TBC 0x00000000
180 #define GPT0_IM 0x00000018
181 #define GPT0_ISS 0x0000001C
182 #define GPT0_ISC 0x00000020
183 #define GPT0_IE 0x00000024
184 #define GPT0_COMP0 0x00000080
185 #define GPT0_COMP1 0x00000084
186 #define GPT0_COMP2 0x00000088
187 #define GPT0_COMP3 0x0000008C
188 #define GPT0_COMP4 0x00000090
189 #define GPT0_COMP5 0x00000094
190 #define GPT0_COMP6 0x00000098
191 #define GPT0_MASK0 0x000000C0
192 #define GPT0_MASK1 0x000000C4
193 #define GPT0_MASK2 0x000000C8
194 #define GPT0_MASK3 0x000000CC
195 #define GPT0_MASK4 0x000000D0
196 #define GPT0_MASK5 0x000000D4
197 #define GPT0_MASK6 0x000000D8
198 #define GPT0_DCT0 0x00000110
199 #define GPT0_DCIS 0x0000011C
201 #if defined(CONFIG_440)
202 #include <asm/ppc440.h>
204 #include <asm/ppc405.h>
207 #include <asm/ppc4xx-sdram.h>
208 #include <asm/ppc4xx-ebc.h>
209 #if !defined(CONFIG_XILINX_440)
210 #include <asm/ppc4xx-uic.h>
214 * Macro for generating register field mnemonics
216 #define PPC_REG_BITS 32
217 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
220 * Elide casts when assembling register mnemonics
223 #define static_cast(type, val) (type)(val)
225 #define static_cast(type, val) (val)
229 * Common stuff for 4xx (405 and 440)
232 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
233 #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
235 #define RESET_VECTOR 0xfffffffc
236 #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
237 cache line aligned data. */
239 #define CPR0_DCR_BASE 0x0C
240 #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
241 #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
243 #define SDR_DCR_BASE 0x0E
244 #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
245 #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
247 #define SDRAM_DCR_BASE 0x10
248 #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
249 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
251 #define EBC_DCR_BASE 0x12
252 #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
253 #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
256 * Macros for indirect DCR access
258 #define mtcpr(reg, d) \
259 do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
260 #define mfcpr(reg, d) \
261 do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
263 #define mtebc(reg, d) \
264 do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
265 #define mfebc(reg, d) \
266 do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
268 #define mtsdram(reg, d) \
269 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
270 #define mfsdram(reg, d) \
271 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
273 #define mtsdr(reg, d) \
274 do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
275 #define mfsdr(reg, d) \
276 do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
282 unsigned long freqDDR;
283 unsigned long freqEBC;
284 unsigned long freqOPB;
285 unsigned long freqPCI;
286 unsigned long freqPLB;
287 unsigned long freqTmrClk;
288 unsigned long freqUART;
289 unsigned long freqProcessor;
290 unsigned long freqVCOHz;
291 unsigned long freqVCOMhz; /* in MHz */
292 unsigned long pciClkSync; /* PCI clock is synchronous */
293 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
294 unsigned long pllExtBusDiv;
295 unsigned long pllFbkDiv;
296 unsigned long pllFwdDiv;
297 unsigned long pllFwdDivA;
298 unsigned long pllFwdDivB;
299 unsigned long pllOpbDiv;
300 unsigned long pllPciDiv;
301 unsigned long pllPlbDiv;
304 static inline u32 get_mcsr(void)
308 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
312 static inline void set_mcsr(u32 val)
314 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
317 int ppc4xx_pci_sync_clock_config(u32 async);
319 #endif /* __ASSEMBLY__ */
321 /* for multi-cpu support */
322 #define NA_OR_UNKNOWN_CPU -1
324 #endif /* __PPC4XX_H__ */