1 /*----------------------------------------------------------------------------+
2 | This source code is dual-licensed. You may use it under the terms of the
3 | GNU General Public License version 2, or under the license below.
5 | This source code has been made available to you by IBM on an AS-IS
6 | basis. Anyone receiving this source is licensed under IBM
7 | copyrights to use it in any way he or she deems fit, including
8 | copying it, modifying it, compiling it, and redistributing it either
9 | with or without modifications. No license under IBM patents or
10 | patent applications is to be implied by the copyright license.
12 | Any user of this software should understand that IBM cannot provide
13 | technical support for this software and will not be responsible for
14 | any consequences resulting from the use of this software.
16 | Any person who transfers this source code or any derivative work
17 | must include the IBM copyright notice, this paragraph, and the
18 | preceding two paragraphs in the transferred software.
20 | COPYRIGHT I B M CORPORATION 1999
21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 +----------------------------------------------------------------------------*/
23 /*----------------------------------------------------------------------------+
25 | File Name: enetemac.h
27 | Function: Header file for the EMAC3 macro on the 405GP.
33 | Date Description of Change BY
34 | --------- --------------------- ---
35 | 29-Apr-99 Created MKW
37 +----------------------------------------------------------------------------*/
38 /*----------------------------------------------------------------------------+
39 | 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
40 | ported to handle 440GP and 440GX multiple EMACs
41 +----------------------------------------------------------------------------*/
43 #ifndef _PPC4XX_ENET_H_
44 #define _PPC4XX_ENET_H_
47 #include "asm/ppc4xx-mal.h"
50 /*-----------------------------------------------------------------------------+
51 | General enternet defines. 802 frames are not supported.
52 +-----------------------------------------------------------------------------*/
53 #define ENET_ADDR_LENGTH 6
54 #define ENET_ARPTYPE 0x806
57 #define ENET_IPTYPE 0x800
58 #define ARP_CACHE_SIZE 5
61 #define NUM_RX_BUFF PKTBUFSRX
64 unsigned char dest_addr[ENET_ADDR_LENGTH];
65 unsigned char source_addr[ENET_ADDR_LENGTH];
67 unsigned char enet_data[1];
71 unsigned long inet_address;
72 unsigned char mac_address[ENET_ADDR_LENGTH];
80 #define MAX_ERR_LOG 10
82 typedef struct emac_stats_st{ /* Statistic Block */
91 short tx_err_log[MAX_ERR_LOG];
92 short rx_err_log[MAX_ERR_LOG];
93 } EMAC_STATS_ST, *EMAC_STATS_PST;
95 /* Structure containing variables used by the shared code (4xx_enet.c) */
96 typedef struct emac_4xx_hw_st {
97 uint32_t hw_addr; /* EMAC offset */
98 uint32_t tah_addr; /* TAH offset */
101 uint32_t original_fc;
103 uint32_t autoneg_failed;
105 volatile mal_desc_t *tx;
106 volatile mal_desc_t *rx;
109 bd_t *bis; /* for eth_init upon mal error */
110 mal_desc_t *alloc_tx_buf;
111 mal_desc_t *alloc_rx_buf;
115 int tbi_compatibility_en;
116 int tbi_compatibility_on;
122 int rx_slot; /* MAL Receive Slot */
123 int rx_i_index; /* Receive Interrupt Queue Index */
124 int rx_u_index; /* Receive User Queue Index */
125 int tx_slot; /* MAL Transmit Slot */
126 int tx_i_index; /* Transmit Interrupt Queue Index */
127 int tx_u_index; /* Transmit User Queue Index */
128 int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
129 int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
130 int is_receiving; /* sync with eth interrupt */
131 int print_speed; /* print speed message upon start */
133 } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
136 #if defined(CONFIG_440GX) || defined(CONFIG_460GT)
137 #define EMAC_NUM_DEV 4
138 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
139 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
140 #define EMAC_NUM_DEV 2
142 #define EMAC_NUM_DEV 1
145 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
146 #define EMAC_STACR_OC_MASK (0x00008000)
148 #define EMAC_STACR_OC_MASK (0x00000000)
152 * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
153 * not have a pin function control (PFC) register to otherwise determine
154 * the bridge configuration.
156 #define EMAC_PHY_MODE_NONE 0
157 #define EMAC_PHY_MODE_NONE_RGMII 1
158 #define EMAC_PHY_MODE_RGMII_NONE 2
159 #define EMAC_PHY_MODE_RGMII_RGMII 3
160 #define EMAC_PHY_MODE_NONE_GMII 4
161 #define EMAC_PHY_MODE_GMII_NONE 5
162 #define EMAC_PHY_MODE_NONE_MII 6
163 #define EMAC_PHY_MODE_MII_NONE 7
165 /* ZMII Bridge Register addresses */
166 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
167 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
168 defined(CONFIG_460EX) || defined(CONFIG_460GT)
169 #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
171 #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
173 #define ZMII0_FER (ZMII0_BASE)
174 #define ZMII0_SSR (ZMII0_BASE + 4)
175 #define ZMII0_SMIISR (ZMII0_BASE + 8)
177 /* ZMII FER Register Bit Definitions */
178 #define ZMII_FER_DIS (0x0)
179 #define ZMII_FER_MDI (0x8)
180 #define ZMII_FER_SMII (0x4)
181 #define ZMII_FER_RMII (0x2)
182 #define ZMII_FER_MII (0x1)
184 #define ZMII_FER_RSVD11 (0x00200000)
185 #define ZMII_FER_RSVD10 (0x00100000)
186 #define ZMII_FER_RSVD14_31 (0x0003FFFF)
188 #define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
191 /* ZMII Speed Selection Register Bit Definitions */
192 #define ZMII0_SSR_SCI (0x4)
193 #define ZMII0_SSR_FSS (0x2)
194 #define ZMII0_SSR_SP (0x1)
195 #define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
197 #define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
200 /* ZMII SMII Status Register Bit Definitions */
201 #define ZMII0_SMIISR_E1 (0x80)
202 #define ZMII0_SMIISR_EC (0x40)
203 #define ZMII0_SMIISR_EN (0x20)
204 #define ZMII0_SMIISR_EJ (0x10)
205 #define ZMII0_SMIISR_EL (0x08)
206 #define ZMII0_SMIISR_ED (0x04)
207 #define ZMII0_SMIISR_ES (0x02)
208 #define ZMII0_SMIISR_EF (0x01)
210 #define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
212 /* RGMII Register Addresses */
213 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
214 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
215 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
216 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
217 #elif defined(CONFIG_405EX)
218 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
220 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
222 #define RGMII_FER (RGMII_BASE + 0x00)
223 #define RGMII_SSR (RGMII_BASE + 0x04)
225 #if defined(CONFIG_460GT)
226 #define RGMII1_BASE_OFFSET 0x100
229 /* RGMII Function Enable (FER) Register Bit Definitions */
230 #define RGMII_FER_DIS (0x00)
231 #define RGMII_FER_RTBI (0x04)
232 #define RGMII_FER_RGMII (0x05)
233 #define RGMII_FER_TBI (0x06)
234 #define RGMII_FER_GMII (0x07)
235 #define RGMII_FER_MII (RGMII_FER_GMII)
237 #define RGMII_FER_V(__x) ((__x - 2) * 4)
239 #define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
241 /* RGMII Speed Selection Register Bit Definitions */
242 #define RGMII_SSR_SP_10MBPS (0x00)
243 #define RGMII_SSR_SP_100MBPS (0x02)
244 #define RGMII_SSR_SP_1000MBPS (0x04)
246 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
247 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
248 defined(CONFIG_405EX)
249 #define RGMII_SSR_V(__x) ((__x) * 8)
251 #define RGMII_SSR_V(__x) ((__x -2) * 8)
254 /*---------------------------------------------------------------------------+
255 | TCP/IP Acceleration Hardware (TAH) 440GX Only
256 +---------------------------------------------------------------------------*/
257 #if defined(CONFIG_440GX)
258 #define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
259 #define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
260 #define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
261 #define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
262 #define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
263 #define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
264 #define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
265 #define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
266 #define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
267 #define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
270 #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
271 #define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
273 #define TAH_REV_RN_V (8)
274 #define TAH_REV_BN_V (0)
276 /* TAH Mode Register */
277 #define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
278 #define TAH_MR_SR (0x40000000) /* Software reset */
279 #define TAH_MR_ST (0x3F000000) /* Send Threshold */
280 #define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
281 #define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
282 #define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
283 #define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
285 #define TAH_MR_ST_V (20)
286 #define TAH_MR_TFS_V (17)
288 #define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
289 #define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
290 #define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
291 #define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
292 #define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
295 /* TAH Segment Size Registers 0:5 */
296 #define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
297 #define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
298 #define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
300 /* TAH Transmit Status Register */
301 #define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
302 #define TAH_TSR_UH (0x40000000) /* Unrecognized header */
303 #define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
304 #define TAH_TSR_IPOP (0x10000000) /* IP option present */
305 #define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
306 #define TAH_TSR_ILTS (0x04000000) /* IP length too short */
307 #define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
308 #define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
309 #define TAH_TSR_TFP (0x00800000) /* TCP flags present */
310 #define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
311 #define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
312 #define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
313 #define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
314 #define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
315 #define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
316 #endif /* CONFIG_440GX */
319 /* Ethernet MAC Regsiter Addresses */
320 #if defined(CONFIG_440)
321 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
322 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
323 defined(CONFIG_460EX) || defined(CONFIG_460GT)
324 #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
326 #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
329 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
330 #define EMAC0_BASE 0xEF600900
332 #define EMAC0_BASE 0xEF600800
336 #if defined(CONFIG_440EPX)
337 #define EMAC1_BASE 0xEF600F00
338 #define EMAC1_MR1 (EMAC1_BASE + 0x04)
341 #define EMAC0_MR0 (EMAC0_BASE)
342 #define EMAC0_MR1 (EMAC0_BASE + 0x04)
343 #define EMAC0_TMR0 (EMAC0_BASE + 0x08)
344 #define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
345 #define EMAC0_RXM (EMAC0_BASE + 0x10)
346 #define EMAC0_ISR (EMAC0_BASE + 0x14)
347 #define EMAC0_IER (EMAC0_BASE + 0x18)
348 #define EMAC0_IAH (EMAC0_BASE + 0x1c)
349 #define EMAC0_IAL (EMAC0_BASE + 0x20)
350 #define EMAC0_PTR (EMAC0_BASE + 0x2c)
351 #define EMAC0_PAUSE_TIME_REG EMAC0_PTR
352 #define EMAC0_IPGVR (EMAC0_BASE + 0x58)
353 #define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
354 #define EMAC0_STACR (EMAC0_BASE + 0x5c)
355 #define EMAC0_TRTR (EMAC0_BASE + 0x60)
356 #define EMAC0_RWMR (EMAC0_BASE + 0x64)
357 #define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
359 /* bit definitions */
361 #define EMAC_MR0_RXI (0x80000000)
362 #define EMAC_MR0_TXI (0x40000000)
363 #define EMAC_MR0_SRST (0x20000000)
364 #define EMAC_MR0_TXE (0x10000000)
365 #define EMAC_MR0_RXE (0x08000000)
366 #define EMAC_MR0_WKE (0x04000000)
368 /* on 440GX EMAC_MR1 has a different layout! */
369 #if defined(CONFIG_440GX) || \
370 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
371 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
372 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
373 defined(CONFIG_405EX)
375 #define EMAC_MR1_FDE (0x80000000)
376 #define EMAC_MR1_ILE (0x40000000)
377 #define EMAC_MR1_VLE (0x20000000)
378 #define EMAC_MR1_EIFC (0x10000000)
379 #define EMAC_MR1_APP (0x08000000)
380 #define EMAC_MR1_RSVD (0x06000000)
381 #define EMAC_MR1_IST (0x01000000)
382 #define EMAC_MR1_MF_1000GPCS (0x00C00000)
383 #define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
384 #define EMAC_MR1_MF_100MBPS (0x00400000)
385 #define EMAC_MR1_RFS_MASK (0x00380000)
386 #define EMAC_MR1_RFS_16K (0x00280000)
387 #define EMAC_MR1_RFS_8K (0x00200000)
388 #define EMAC_MR1_RFS_4K (0x00180000)
389 #define EMAC_MR1_RFS_2K (0x00100000)
390 #define EMAC_MR1_RFS_1K (0x00080000)
391 #define EMAC_MR1_TX_FIFO_MASK (0x00070000)
392 #define EMAC_MR1_TX_FIFO_16K (0x00050000)
393 #define EMAC_MR1_TX_FIFO_8K (0x00040000)
394 #define EMAC_MR1_TX_FIFO_4K (0x00030000)
395 #define EMAC_MR1_TX_FIFO_2K (0x00020000)
396 #define EMAC_MR1_TX_FIFO_1K (0x00010000)
397 #define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
398 #define EMAC_MR1_MWSW (0x00007000)
399 #define EMAC_MR1_JUMBO_ENABLE (0x00000800)
400 #define EMAC_MR1_IPPA (0x000007c0)
401 #define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
402 #define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
403 #define EMAC_MR1_OBCI_GT100 (0x00000020)
404 #define EMAC_MR1_OBCI_100 (0x00000018)
405 #define EMAC_MR1_OBCI_83 (0x00000010)
406 #define EMAC_MR1_OBCI_66 (0x00000008)
407 #define EMAC_MR1_RSVD1 (0x00000007)
408 #else /* defined(CONFIG_440GX) */
409 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
410 #define EMAC_MR1_FDE 0x80000000
411 #define EMAC_MR1_ILE 0x40000000
412 #define EMAC_MR1_VLE 0x20000000
413 #define EMAC_MR1_EIFC 0x10000000
414 #define EMAC_MR1_APP 0x08000000
415 #define EMAC_MR1_AEMI 0x02000000
416 #define EMAC_MR1_IST 0x01000000
417 #define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
418 #define EMAC_MR1_MF_100MBPS 0x00400000
419 #define EMAC_MR1_RFS_MASK 0x00300000
420 #define EMAC_MR1_RFS_4K 0x00300000
421 #define EMAC_MR1_RFS_2K 0x00200000
422 #define EMAC_MR1_RFS_1K 0x00100000
423 #define EMAC_MR1_RFS_512 0x00000000
424 #define EMAC_MR1_TX_FIFO_MASK 0x000c0000
425 #define EMAC_MR1_TX_FIFO_2K 0x00080000
426 #define EMAC_MR1_TX_FIFO_1K 0x00040000
427 #define EMAC_MR1_TX_FIFO_512 0x00000000
428 #define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
429 #define EMAC_MR1_TR0_MULTI 0x00008000
430 #define EMAC_MR1_TR1_DEPEND 0x00004000
431 #define EMAC_MR1_TR1_MULTI 0x00002000
432 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
433 #define EMAC_MR1_JUMBO_ENABLE 0x00001000
434 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
435 #endif /* defined(CONFIG_440GX) */
437 #define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
438 #if defined(CONFIG_405EZ)
439 /* 405EZ only supports 512 bytes fifos */
440 #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
442 /* Set receive fifo to 4k and tx fifo to 2k */
443 #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
446 /* Transmit Mode Register 0 */
447 #define EMAC_TMR0_GNP0 (0x80000000)
448 #define EMAC_TMR0_GNP1 (0x40000000)
449 #define EMAC_TMR0_GNPD (0x20000000)
450 #define EMAC_TMR0_FC (0x10000000)
452 /* Receive Mode Register */
453 #define EMAC_RMR_SP (0x80000000)
454 #define EMAC_RMR_SFCS (0x40000000)
455 #define EMAC_RMR_ARRP (0x20000000)
456 #define EMAC_RMR_ARP (0x10000000)
457 #define EMAC_RMR_AROP (0x08000000)
458 #define EMAC_RMR_ARPI (0x04000000)
459 #define EMAC_RMR_PPP (0x02000000)
460 #define EMAC_RMR_PME (0x01000000)
461 #define EMAC_RMR_PMME (0x00800000)
462 #define EMAC_RMR_IAE (0x00400000)
463 #define EMAC_RMR_MIAE (0x00200000)
464 #define EMAC_RMR_BAE (0x00100000)
465 #define EMAC_RMR_MAE (0x00080000)
467 /* Interrupt Status & enable Regs */
468 #define EMAC_ISR_OVR (0x02000000)
469 #define EMAC_ISR_PP (0x01000000)
470 #define EMAC_ISR_BP (0x00800000)
471 #define EMAC_ISR_RP (0x00400000)
472 #define EMAC_ISR_SE (0x00200000)
473 #define EMAC_ISR_SYE (0x00100000)
474 #define EMAC_ISR_BFCS (0x00080000)
475 #define EMAC_ISR_PTLE (0x00040000)
476 #define EMAC_ISR_ORE (0x00020000)
477 #define EMAC_ISR_IRE (0x00010000)
478 #define EMAC_ISR_DBDM (0x00000200)
479 #define EMAC_ISR_DB0 (0x00000100)
480 #define EMAC_ISR_SE0 (0x00000080)
481 #define EMAC_ISR_TE0 (0x00000040)
482 #define EMAC_ISR_DB1 (0x00000020)
483 #define EMAC_ISR_SE1 (0x00000010)
484 #define EMAC_ISR_TE1 (0x00000008)
485 #define EMAC_ISR_MOS (0x00000002)
486 #define EMAC_ISR_MOF (0x00000001)
488 /* STA CONTROL REG */
489 #define EMAC_STACR_OC (0x00008000)
490 #define EMAC_STACR_PHYE (0x00004000)
492 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
493 #define EMAC_STACR_INDIRECT_MODE (0x00002000)
494 #define EMAC_STACR_WRITE (0x00000800) /* $BUC */
495 #define EMAC_STACR_READ (0x00001000) /* $BUC */
496 #define EMAC_STACR_OP_MASK (0x00001800)
497 #define EMAC_STACR_MDIO_ADDR (0x00000000)
498 #define EMAC_STACR_MDIO_WRITE (0x00000800)
499 #define EMAC_STACR_MDIO_READ (0x00001800)
500 #define EMAC_STACR_MDIO_READ_INC (0x00001000)
502 #define EMAC_STACR_WRITE (0x00002000)
503 #define EMAC_STACR_READ (0x00001000)
506 #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
507 #define EMAC_STACR_CLK_66MHZ (0x00000400)
508 #define EMAC_STACR_CLK_100MHZ (0x00000C00)
510 /* Transmit Request Threshold Register */
511 #define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
512 #define EMAC_TRTR_192 (0x10000000)
513 #define EMAC_TRTR_128 (0x01000000)
515 /* the follwing defines are for the MadMAL status and control registers. */
516 /* For bits 0..5 look at the mal.h file */
517 #define EMAC_TX_CTRL_GFCS (0x0200)
518 #define EMAC_TX_CTRL_GP (0x0100)
519 #define EMAC_TX_CTRL_ISA (0x0080)
520 #define EMAC_TX_CTRL_RSA (0x0040)
521 #define EMAC_TX_CTRL_IVT (0x0020)
522 #define EMAC_TX_CTRL_RVT (0x0010)
524 #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
526 #define EMAC_TX_ST_BFCS (0x0200)
527 #define EMAC_TX_ST_BPP (0x0100)
528 #define EMAC_TX_ST_LCS (0x0080)
529 #define EMAC_TX_ST_ED (0x0040)
530 #define EMAC_TX_ST_EC (0x0020)
531 #define EMAC_TX_ST_LC (0x0010)
532 #define EMAC_TX_ST_MC (0x0008)
533 #define EMAC_TX_ST_SC (0x0004)
534 #define EMAC_TX_ST_UR (0x0002)
535 #define EMAC_TX_ST_SQE (0x0001)
537 #define EMAC_TX_ST_DEFAULT (0x03F3)
540 /* madmal receive status / Control bits */
542 #define EMAC_RX_ST_OE (0x0200)
543 #define EMAC_RX_ST_PP (0x0100)
544 #define EMAC_RX_ST_BP (0x0080)
545 #define EMAC_RX_ST_RP (0x0040)
546 #define EMAC_RX_ST_SE (0x0020)
547 #define EMAC_RX_ST_AE (0x0010)
548 #define EMAC_RX_ST_BFCS (0x0008)
549 #define EMAC_RX_ST_PTL (0x0004)
550 #define EMAC_RX_ST_ORE (0x0002)
551 #define EMAC_RX_ST_IRE (0x0001)
552 /* all the errors we care about */
553 #define EMAC_RX_ERRORS (0x03FF)
555 #endif /* _PPC4XX_ENET_H_ */