arch/powerpc/include/asm/opal.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * PowerNV OPAL definitions.
   4  *
   5  * Copyright 2011 IBM Corp.
   6  */
   7
   8 #ifndef _ASM_POWERPC_OPAL_H
   9 #define _ASM_POWERPC_OPAL_H
  10
  11 #include <asm/opal-api.h>
  12
  13 #ifndef __ASSEMBLY__
  14
  15 #include <linux/notifier.h>
  16
  17 /* We calculate number of sg entries based on PAGE_SIZE */
  18 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
  19
  20 /* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */
  21 #define OPAL_BUSY_DELAY_MS      10
  22
  23 /* /sys/firmware/opal */
  24 extern struct kobject *opal_kobj;
  25
  26 /* /ibm,opal */
  27 extern struct device_node *opal_node;
  28
  29 /* API functions */
  30 int64_t opal_invalid_call(void);
  31 int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
  32 int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
  33                         uint64_t bdf);
  34 int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
  35                         uint64_t lpcr);
  36 int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
  37                         uint64_t addr, uint64_t PE_mask);
  38 int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
  39                                 uint64_t PE_handle);
  40 int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
  41                         uint64_t rate_phys, uint32_t size);
  42 int64_t opal_console_write(int64_t term_number, __be64 *length,
  43                            const uint8_t *buffer);
  44 int64_t opal_console_read(int64_t term_number, __be64 *length,
  45                           uint8_t *buffer);
  46 int64_t opal_console_write_buffer_space(int64_t term_number,
  47                                         __be64 *length);
  48 int64_t opal_console_flush(int64_t term_number);
  49 int64_t opal_rtc_read(__be32 *year_month_day,
  50                       __be64 *hour_minute_second_millisecond);
  51 int64_t opal_rtc_write(uint32_t year_month_day,
  52                        uint64_t hour_minute_second_millisecond);
  53 int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
  54 int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
  55                        uint32_t hour_min);
  56 int64_t opal_cec_power_down(uint64_t request);
  57 int64_t opal_cec_reboot(void);
  58 int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
  59 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
  60 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
  61 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
  62 int64_t opal_poll_events(__be64 *outstanding_event_mask);
  63 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
  64                                     uint64_t tce_mem_size);
  65 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
  66                                     uint64_t tce_mem_size);
  67 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
  68                                   uint64_t offset, uint8_t *data);
  69 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
  70                                        uint64_t offset, __be16 *data);
  71 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
  72                                   uint64_t offset, __be32 *data);
  73 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
  74                                    uint64_t offset, uint8_t data);
  75 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
  76                                         uint64_t offset, uint16_t data);
  77 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
  78                                    uint64_t offset, uint32_t data);
  79 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
  80 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
  81 int64_t opal_register_exception_handler(uint64_t opal_exception,
  82                                         uint64_t handler_address,
  83                                         uint64_t glue_cache_line);
  84 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
  85                                    uint8_t *freeze_state,
  86                                    __be16 *pci_error_type,
  87                                    __be64 *phb_status);
  88 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
  89                                   uint64_t eeh_action_token);
  90 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
  91                                 uint64_t eeh_action_token);
  92 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
  93                             uint32_t func, uint64_t addr, uint64_t mask);
  94 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
  95
  96
  97
  98 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
  99                                  uint16_t window_num, uint16_t enable);
 100 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 101                                     uint16_t window_num,
 102                                     uint64_t starting_real_address,
 103                                     uint64_t starting_pci_address,
 104                                     uint64_t size);
 105 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 106                                     uint16_t window_type, uint16_t window_num,
 107                                     uint16_t segment_num);
 108 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 109                                       uint64_t ivt_addr, uint64_t ivt_len,
 110                                       uint64_t reject_array_addr,
 111                                       uint64_t peltv_addr);
 112 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 113                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 114                         uint8_t pe_action);
 115 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 116                            uint8_t state);
 117 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 118 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 119                                 uint32_t state);
 120 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 121                                   uint8_t *p_bit, uint8_t *q_bit);
 122 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 123                                   uint8_t p_bit, uint8_t q_bit);
 124 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 125 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 126                              uint32_t xive_num);
 127 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 128                              __be32 *interrupt_source_number);
 129 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 130                         uint8_t msi_range, __be32 *msi_address,
 131                         __be32 *message_data);
 132 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 133                         uint32_t xive_num, uint8_t msi_range,
 134                         __be64 *msi_address, __be32 *message_data);
 135 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 136 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 137 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 138 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 139                                    uint16_t tce_levels, uint64_t tce_table_addr,
 140                                    uint64_t tce_table_size, uint64_t tce_page_size);
 141 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 142                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 143                                         uint64_t pci_mem_size);
 144 int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
 145
 146 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 147                                    uint64_t diag_buffer_len);
 148 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 149                                    uint64_t diag_buffer_len);
 150 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 151                                     uint64_t diag_buffer_len);
 152 int64_t opal_pci_fence_phb(uint64_t phb_id);
 153 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 154 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 155 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 156 int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
 157 int64_t opal_get_dpo_status(__be64 *dpo_timeout);
 158 int64_t opal_set_system_attention_led(uint8_t led_action);
 159 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
 160                             __be16 *pci_error_type, __be16 *severity);
 161 int64_t opal_pci_poll(uint64_t id);
 162 int64_t opal_return_cpu(void);
 163 int64_t opal_check_token(uint64_t token);
 164 int64_t opal_reinit_cpus(uint64_t flags);
 165
 166 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 167 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
 168
 169 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 170                        uint32_t addr, uint32_t data, uint32_t sz);
 171 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 172                       uint32_t addr, __be32 *data, uint32_t sz);
 173
 174 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
 175 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
 176 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
 177 int64_t opal_send_ack_elog(uint64_t log_id);
 178 void opal_resend_pending_logs(void);
 179
 180 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 181 int64_t opal_manage_flash(uint8_t op);
 182 int64_t opal_update_flash(uint64_t blk_list);
 183 int64_t opal_dump_init(uint8_t dump_type);
 184 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
 185 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
 186 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
 187 int64_t opal_dump_ack(uint32_t dump_id);
 188 int64_t opal_dump_resend_notification(void);
 189
 190 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
 191 int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
 192                                         uint64_t num_lines);
 193 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
 194 int64_t opal_sync_host_reboot(void);
 195 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 196                 uint64_t length);
 197 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 198                 uint64_t length);
 199 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 200 int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
 201 int64_t opal_handle_hmi(void);
 202 int64_t opal_handle_hmi2(__be64 *out_flags);
 203 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
 204 int64_t opal_unregister_dump_region(uint32_t id);
 205 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
 206 int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
 207 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
 208 int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
 209 int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
 210 int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
 211                 uint64_t msg_len);
 212 int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
 213                 uint64_t *msg_len);
 214 int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
 215                          struct opal_i2c_request *oreq);
 216 int64_t opal_prd_msg(struct opal_prd_msg *msg);
 217 int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
 218                           __be64 *led_value, __be64 *max_led_type);
 219 int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
 220                           const u64 led_value, __be64 *max_led_type);
 221
 222 int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
 223                 uint64_t size, uint64_t token);
 224 int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
 225                 uint64_t size, uint64_t token);
 226 int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
 227                 uint64_t token);
 228 int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
 229 int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
 230 int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
 231 int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
 232                                  uint64_t data);
 233 int64_t opal_pci_poll2(uint64_t id, uint64_t data);
 234
 235 int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
 236 int64_t opal_int_set_cppr(uint8_t cppr);
 237 int64_t opal_int_eoi(uint32_t xirr);
 238 int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
 239 int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
 240                           uint32_t pe_num, uint32_t tce_size,
 241                           uint64_t dma_addr, uint32_t npages);
 242 int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
 243 int64_t opal_xive_reset(uint64_t version);
 244 int64_t opal_xive_get_irq_info(uint32_t girq,
 245                                __be64 *out_flags,
 246                                __be64 *out_eoi_page,
 247                                __be64 *out_trig_page,
 248                                __be32 *out_esb_shift,
 249                                __be32 *out_src_chip);
 250 int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
 251                                  uint8_t *out_prio, __be32 *out_lirq);
 252 int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
 253                                  uint32_t lirq);
 254 int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
 255                                  __be64 *out_qpage,
 256                                  __be64 *out_qsize,
 257                                  __be64 *out_qeoi_page,
 258                                  __be32 *out_escalate_irq,
 259                                  __be64 *out_qflags);
 260 int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
 261                                  uint64_t qpage,
 262                                  uint64_t qsize,
 263                                  uint64_t qflags);
 264 int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
 265 int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
 266 int64_t opal_xive_free_vp_block(uint64_t vp);
 267 int64_t opal_xive_get_vp_info(uint64_t vp,
 268                               __be64 *out_flags,
 269                               __be64 *out_cam_value,
 270                               __be64 *out_report_cl_pair,
 271                               __be32 *out_chip_id);
 272 int64_t opal_xive_set_vp_info(uint64_t vp,
 273                               uint64_t flags,
 274                               uint64_t report_cl_pair);
 275 int64_t opal_xive_allocate_irq_raw(uint32_t chip_id);
 276 int64_t opal_xive_free_irq(uint32_t girq);
 277 int64_t opal_xive_sync(uint32_t type, uint32_t id);
 278 int64_t opal_xive_dump(uint32_t type, uint32_t id);
 279 int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
 280                                   __be32 *out_qtoggle,
 281                                   __be32 *out_qindex);
 282 int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
 283                                   uint32_t qtoggle,
 284                                   uint32_t qindex);
 285 int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
 286
 287 int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
 288                                                         uint64_t cpu_pir);
 289 int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
 290 int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
 291
 292 int opal_get_powercap(u32 handle, int token, u32 *pcap);
 293 int opal_set_powercap(u32 handle, int token, u32 pcap);
 294 int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
 295 int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
 296 int opal_sensor_group_clear(u32 group_hndl, int token);
 297 int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
 298 int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
 299
 300 s64 opal_signal_system_reset(s32 cpu);
 301 s64 opal_quiesce(u64 shutdown_type, s32 cpu);
 302
 303 /* Internal functions */
 304 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 305                                    int depth, void *data);
 306 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
 307                                  const char *uname, int depth, void *data);
 308 extern void opal_configure_cores(void);
 309
 310 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 311 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 312 extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
 313 extern int opal_flush_chars(uint32_t vtermno, bool wait);
 314 extern int opal_flush_console(uint32_t vtermno);
 315
 316 extern void hvc_opal_init_early(void);
 317
 318 extern int opal_notifier_register(struct notifier_block *nb);
 319 extern int opal_notifier_unregister(struct notifier_block *nb);
 320
 321 extern int opal_message_notifier_register(enum opal_msg_type msg_type,
 322                                                 struct notifier_block *nb);
 323 extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
 324                                             struct notifier_block *nb);
 325 extern void opal_notifier_enable(void);
 326 extern void opal_notifier_disable(void);
 327 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 328
 329 extern int opal_async_get_token_interruptible(void);
 330 extern int opal_async_release_token(int token);
 331 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
 332 extern int opal_async_wait_response_interruptible(uint64_t token,
 333                 struct opal_msg *msg);
 334 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
 335 extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
 336 extern int sensor_group_enable(u32 grp_hndl, bool enable);
 337
 338 struct rtc_time;
 339 extern time64_t opal_get_boot_time(void);
 340 extern void opal_nvram_init(void);
 341 extern void opal_flash_update_init(void);
 342 extern void opal_flash_update_print_message(void);
 343 extern int opal_elog_init(void);
 344 extern void opal_platform_dump_init(void);
 345 extern void opal_sys_param_init(void);
 346 extern void opal_msglog_init(void);
 347 extern void opal_msglog_sysfs_init(void);
 348 extern int opal_async_comp_init(void);
 349 extern int opal_sensor_init(void);
 350 extern int opal_hmi_handler_init(void);
 351 extern int opal_event_init(void);
 352 int opal_power_control_init(void);
 353
 354 extern int opal_machine_check(struct pt_regs *regs);
 355 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
 356 extern int opal_hmi_exception_early(struct pt_regs *regs);
 357 extern int opal_hmi_exception_early2(struct pt_regs *regs);
 358 extern int opal_handle_hmi_exception(struct pt_regs *regs);
 359
 360 extern void opal_shutdown(void);
 361 extern int opal_resync_timebase(void);
 362
 363 extern void opal_lpc_init(void);
 364
 365 extern void opal_kmsg_init(void);
 366
 367 extern int opal_event_request(unsigned int opal_event_nr);
 368
 369 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
 370                                              unsigned long vmalloc_size);
 371 void opal_free_sg_list(struct opal_sg_list *sg);
 372
 373 extern int opal_error_code(int rc);
 374
 375 ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
 376
 377 static inline int opal_get_async_rc(struct opal_msg msg)
 378 {
 379         if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
 380                 return OPAL_PARAMETER;
 381         else
 382                 return be64_to_cpu(msg.params[1]);
 383 }
 384
 385 void opal_wake_poller(void);
 386
 387 void opal_powercap_init(void);
 388 void opal_psr_init(void);
 389 void opal_sensor_groups_init(void);
 390
 391 #endif /* __ASSEMBLY__ */
 392
 393 #endif /* _ASM_POWERPC_OPAL_H */