1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004-2011 Freescale Semiconductor, Inc.
5 * MPC83xx Internal Memory Map
8 * Dave Liu <daveliu@freescale.com>
9 * Tanya Jiang <tanya.jiang@freescale.com>
10 * Mandy Lavi <mandy.lavi@freescale.com>
11 * Eran Liberty <liberty@freescale.com>
13 #ifndef __IMMAP_83xx__
14 #define __IMMAP_83xx__
16 #include <fsl_immap.h>
17 #include <asm/types.h>
18 #include <asm/fsl_i2c.h>
19 #include <asm/mpc8xxx_spi.h>
20 #include <asm/fsl_lbc.h>
21 #include <asm/fsl_dma.h>
26 typedef struct law83xx {
27 u32 bar; /* LBIU local access window base address register */
28 u32 ar; /* LBIU local access window attribute register */
32 * System configuration registers
34 typedef struct sysconf83xx {
35 u32 immrbar; /* Internal memory map base address register */
37 u32 altcbar; /* Alternate configuration base address register */
39 law83xx_t lblaw[4]; /* LBIU local access window */
41 law83xx_t pcilaw[2]; /* PCI local access window */
43 law83xx_t pcielaw[2]; /* PCI Express local access window */
45 law83xx_t ddrlaw[2]; /* DDR local access window */
47 u32 sgprl; /* System General Purpose Register Low */
48 u32 sgprh; /* System General Purpose Register High */
49 u32 spridr; /* System Part and Revision ID Register */
51 u32 spcr; /* System Priority Configuration Register */
52 u32 sicrl; /* System I/O Configuration Register Low */
53 u32 sicrh; /* System I/O Configuration Register High */
55 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
56 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
57 u32 ddrcdr; /* DDR Control Driver Register */
58 u32 ddrdsr; /* DDR Debug Status Register */
59 u32 obir; /* Output Buffer Impedance Register */
61 u32 pecr1; /* PCI Express control register 1 */
62 #if defined(CONFIG_MPC830x)
63 u32 sdhccr; /* eSDHC Control Registers for MPC830x */
65 u32 pecr2; /* PCI Express control register 2 */
67 #if defined(CONFIG_MPC8309)
78 * Watch Dog Timer (WDT) Registers
80 typedef struct wdt83xx {
82 u32 swcrr; /* System watchdog control register */
83 u32 swcnr; /* System watchdog count register */
85 u16 swsrr; /* System watchdog service register */
90 * RTC/PIT Module Registers
92 typedef struct rtclk83xx {
93 u32 cnr; /* control register */
94 u32 ldr; /* load register */
95 u32 psr; /* prescale register */
96 u32 ctr; /* counter value field register */
97 u32 evr; /* event register */
98 u32 alr; /* alarm register */
103 * Global timer module
105 typedef struct gtm83xx {
106 u8 cfr1; /* Timer1/2 Configuration */
108 u8 cfr2; /* Timer3/4 Configuration */
110 u16 mdr1; /* Timer1 Mode Register */
111 u16 mdr2; /* Timer2 Mode Register */
112 u16 rfr1; /* Timer1 Reference Register */
113 u16 rfr2; /* Timer2 Reference Register */
114 u16 cpr1; /* Timer1 Capture Register */
115 u16 cpr2; /* Timer2 Capture Register */
116 u16 cnr1; /* Timer1 Counter Register */
117 u16 cnr2; /* Timer2 Counter Register */
118 u16 mdr3; /* Timer3 Mode Register */
119 u16 mdr4; /* Timer4 Mode Register */
120 u16 rfr3; /* Timer3 Reference Register */
121 u16 rfr4; /* Timer4 Reference Register */
122 u16 cpr3; /* Timer3 Capture Register */
123 u16 cpr4; /* Timer4 Capture Register */
124 u16 cnr3; /* Timer3 Counter Register */
125 u16 cnr4; /* Timer4 Counter Register */
126 u16 evr1; /* Timer1 Event Register */
127 u16 evr2; /* Timer2 Event Register */
128 u16 evr3; /* Timer3 Event Register */
129 u16 evr4; /* Timer4 Event Register */
130 u16 psr1; /* Timer1 Prescaler Register */
131 u16 psr2; /* Timer2 Prescaler Register */
132 u16 psr3; /* Timer3 Prescaler Register */
133 u16 psr4; /* Timer4 Prescaler Register */
138 * Integrated Programmable Interrupt Controller
140 typedef struct ipic83xx {
141 u32 sicfr; /* System Global Interrupt Configuration Register */
142 u32 sivcr; /* System Global Interrupt Vector Register */
143 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
144 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
145 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
146 u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
147 u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
148 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
149 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
150 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
151 u32 sicnr; /* System Internal Interrupt Control Register */
152 u32 sepnr; /* System External Interrupt Pending Register */
153 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
154 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
155 u32 semsr; /* System External Interrupt Mask Register */
156 u32 secnr; /* System External Interrupt Control Register */
157 u32 sersr; /* System Error Status Register */
158 u32 sermr; /* System Error Mask Register */
159 u32 sercr; /* System Error Control Register */
160 u32 sepcr; /* System External Interrupt Polarity Control Register */
161 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
162 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
163 u32 sefcr; /* System External Interrupt Force Register */
164 u32 serfr; /* System Error Force Register */
165 u32 scvcr; /* System Critical Interrupt Vector Register */
166 u32 smvcr; /* System Management Interrupt Vector Register */
171 * System Arbiter Registers
173 typedef struct arbiter83xx {
174 u32 acr; /* Arbiter Configuration Register */
175 u32 atr; /* Arbiter Timers Register */
177 u32 aer; /* Arbiter Event Register */
178 u32 aidr; /* Arbiter Interrupt Definition Register */
179 u32 amr; /* Arbiter Mask Register */
180 u32 aeatr; /* Arbiter Event Attributes Register */
181 u32 aeadr; /* Arbiter Event Address Register */
182 u32 aerr; /* Arbiter Event Response Register */
189 typedef struct reset83xx {
190 u32 rcwl; /* Reset Configuration Word Low Register */
191 u32 rcwh; /* Reset Configuration Word High Register */
193 u32 rsr; /* Reset Status Register */
194 u32 rmr; /* Reset Mode Register */
195 u32 rpr; /* Reset protection Register */
196 u32 rcr; /* Reset Control Register */
197 u32 rcer; /* Reset Control Enable Register */
204 typedef struct clk83xx {
205 u32 spmr; /* system PLL mode Register */
206 u32 occr; /* output clock control Register */
207 u32 sccr; /* system clock control Register */
212 * Power Management Control Module
214 typedef struct pmc83xx {
215 u32 pmccr; /* PMC Configuration Register */
216 u32 pmcer; /* PMC Event Register */
217 u32 pmcmr; /* PMC Mask Register */
218 u32 pmccr1; /* PMC Configuration Register 1 */
219 u32 pmccr2; /* PMC Configuration Register 2 */
224 * General purpose I/O module
226 typedef struct gpio83xx {
227 u32 dir; /* direction register */
228 u32 odr; /* open drain register */
229 u32 dat; /* data register */
230 u32 ier; /* interrupt event register */
231 u32 imr; /* interrupt mask register */
232 u32 icr; /* external interrupt control register */
237 * QE Ports Interrupts Registers
239 typedef struct qepi83xx {
241 u32 qepier; /* QE Ports Interrupt Event Register */
242 u32 qepimr; /* QE Ports Interrupt Mask Register */
243 u32 qepicr; /* QE Ports Interrupt Control Register */
248 * QE Parallel I/O Ports
250 typedef struct gpio_n {
251 u32 podr; /* Open Drain Register */
252 u32 pdat; /* Data Register */
253 u32 dir1; /* direction register 1 */
254 u32 dir2; /* direction register 2 */
255 u32 ppar1; /* Pin Assignment Register 1 */
256 u32 ppar2; /* Pin Assignment Register 2 */
259 typedef struct qegpio83xx {
260 gpio_n_t ioport[0x7];
265 * QE Secondary Bus Access Windows
267 typedef struct qesba83xx {
268 u32 lbmcsar; /* Local bus memory controller start address */
269 u32 sdmcsar; /* Secondary DDR memory controller start address */
271 u32 lbmcear; /* Local bus memory controller end address */
272 u32 sdmcear; /* Secondary DDR memory controller end address */
274 u32 lbmcar; /* Local bus memory controller attributes */
275 u32 sdmcar; /* Secondary DDR memory controller attributes */
280 * DDR Memory Controller Memory Map for DDR1
281 * The structure of DDR2, or DDR3 is defined in fsl_immap.h
283 #if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
284 typedef struct ddr_cs_bnds {
289 typedef struct ddr83xx {
290 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
292 u32 cs_config[4]; /* Chip Select x Configuration */
294 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
295 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
296 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
297 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
298 u32 sdram_cfg; /* SDRAM Control Configuration */
299 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
300 u32 sdram_mode; /* SDRAM Mode Configuration */
301 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
302 u32 sdram_md_cntl; /* SDRAM Mode Control */
303 u32 sdram_interval; /* SDRAM Interval Configuration */
304 u32 ddr_data_init; /* SDRAM Data Initialization */
306 u32 sdram_clk_cntl; /* SDRAM Clock Control */
308 u32 ddr_init_addr; /* DDR training initialization address */
309 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
311 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
312 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
314 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
315 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
316 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
318 u32 capture_data_hi; /* Memory Data Path Read Capture High */
319 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
320 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
322 u32 err_detect; /* Memory Error Detect */
323 u32 err_disable; /* Memory Error Disable */
324 u32 err_int_en; /* Memory Error Interrupt Enable */
325 u32 capture_attributes; /* Memory Error Attributes Capture */
326 u32 capture_address; /* Memory Error Address Capture */
327 u32 capture_ext_address;/* Memory Error Extended Address Capture */
328 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
338 typedef struct duart83xx {
339 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
340 u8 uier_udmb; /* combined register for UIER and UDMB */
341 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
342 u8 ulcr; /* line control register */
343 u8 umcr; /* MODEM control register */
344 u8 ulsr; /* line status register */
345 u8 umsr; /* MODEM status register */
346 u8 uscr; /* scratch register */
348 u8 udsr; /* DMA status register */
356 typedef struct dma83xx {
357 u32 res0[0xC]; /* 0x0-0x29 reseverd */
358 u32 omisr; /* 0x30 Outbound message interrupt status register */
359 u32 omimr; /* 0x34 Outbound message interrupt mask register */
360 u32 res1[0x6]; /* 0x38-0x49 reserved */
361 u32 imr0; /* 0x50 Inbound message register 0 */
362 u32 imr1; /* 0x54 Inbound message register 1 */
363 u32 omr0; /* 0x58 Outbound message register 0 */
364 u32 omr1; /* 0x5C Outbound message register 1 */
365 u32 odr; /* 0x60 Outbound doorbell register */
366 u32 res2; /* 0x64-0x67 reserved */
367 u32 idr; /* 0x68 Inbound doorbell register */
368 u32 res3[0x5]; /* 0x6C-0x79 reserved */
369 u32 imisr; /* 0x80 Inbound message interrupt status register */
370 u32 imimr; /* 0x84 Inbound message interrupt mask register */
371 u32 res4[0x1E]; /* 0x88-0x99 reserved */
372 struct fsl_dma dma[4];
376 * PCI Software Configuration Registers
378 typedef struct pciconf83xx {
386 * PCI Outbound Translation Register
388 typedef struct pci_outbound_window {
400 typedef struct ios83xx {
410 * PCI Controller Control and Status Registers
412 typedef struct pcictrl83xx {
448 typedef struct usb83xx {
455 typedef struct tsec83xx {
462 typedef struct security83xx {
469 struct pex_inbound_window {
476 struct pex_outbound_window {
483 struct pex_csb_bridge {
514 u32 pex_int_apio_vec1;
515 u32 pex_int_apio_vec2;
517 u32 pex_int_ppio_vec1;
518 u32 pex_int_ppio_vec2;
519 u32 pex_int_wdma_vec1;
520 u32 pex_int_wdma_vec2;
521 u32 pex_int_rdma_vec1;
522 u32 pex_int_rdma_vec2;
523 u32 pex_int_misc_vec;
525 u32 pex_int_axi_pio_enb;
526 u32 pex_int_axi_wdma_enb;
527 u32 pex_int_axi_rdma_enb;
528 u32 pex_int_axi_misc_enb;
529 u32 pex_int_axi_pio_stat;
530 u32 pex_int_axi_wdma_stat;
531 u32 pex_int_axi_rdma_stat;
532 u32 pex_int_axi_misc_stat;
534 struct pex_outbound_window pex_outbound_win[4];
541 struct pex_inbound_window pex_inbound_win[4];
544 typedef struct pex83xx {
545 u8 pex_cfg_header[0x404];
548 u32 pex_ack_replay_timeout;
555 u32 pex_aspm_req_timer;
557 u32 pex_ssvid_update;
567 u32 pex_pme_to_ack_tor;
569 u32 pex_ss_intr_mask;
571 struct pex_csb_bridge bridge;
578 typedef struct sata83xx {
585 typedef struct sdhc83xx {
592 typedef struct serdes83xx {
606 typedef struct rom83xx {
607 #if defined(CONFIG_MPC8309)
617 typedef struct tdm83xx {
624 typedef struct tdmdmac83xx {
628 #if defined(CONFIG_MPC834x)
629 typedef struct immap {
630 sysconf83xx_t sysconf; /* System configuration */
631 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
632 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
633 rtclk83xx_t pit; /* Periodic Interval Timer */
634 gtm83xx_t gtm[2]; /* Global Timers Module */
635 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
636 arbiter83xx_t arbiter; /* System Arbiter Registers */
637 reset83xx_t reset; /* Reset Module */
638 clk83xx_t clk; /* System Clock Module */
639 pmc83xx_t pmc; /* Power Management Control Module */
640 gpio83xx_t gpio[2]; /* General purpose I/O module */
645 #if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
646 struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
648 ddr83xx_t ddr; /* DDR Memory Controller Memory */
650 fsl_i2c_t i2c[2]; /* I2C Controllers */
652 duart83xx_t duart[2]; /* DUART */
654 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
656 spi8xxx_t spi; /* Serial Peripheral Interface */
657 dma83xx_t dma; /* DMA */
658 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
659 ios83xx_t ios; /* Sequencer */
660 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
665 security83xx_t security;
669 #ifndef CONFIG_MPC834x
670 #ifdef CONFIG_HAS_FSL_MPH_USB
671 #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
672 #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
674 #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
675 #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
678 #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
679 #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
682 #elif defined(CONFIG_MPC8313)
683 typedef struct immap {
684 sysconf83xx_t sysconf; /* System configuration */
685 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
686 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
687 rtclk83xx_t pit; /* Periodic Interval Timer */
688 gtm83xx_t gtm[2]; /* Global Timers Module */
689 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
690 arbiter83xx_t arbiter; /* System Arbiter Registers */
691 reset83xx_t reset; /* Reset Module */
692 clk83xx_t clk; /* System Clock Module */
693 pmc83xx_t pmc; /* Power Management Control Module */
694 gpio83xx_t gpio[1]; /* General purpose I/O module */
696 ddr83xx_t ddr; /* DDR Memory Controller Memory */
697 fsl_i2c_t i2c[2]; /* I2C Controllers */
699 duart83xx_t duart[2]; /* DUART */
701 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
703 spi8xxx_t spi; /* Serial Peripheral Interface */
704 dma83xx_t dma; /* DMA */
705 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
707 ios83xx_t ios; /* Sequencer */
708 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
713 security83xx_t security;
717 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
718 typedef struct immap {
719 sysconf83xx_t sysconf; /* System configuration */
720 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
721 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
722 rtclk83xx_t pit; /* Periodic Interval Timer */
723 gtm83xx_t gtm[2]; /* Global Timers Module */
724 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
725 arbiter83xx_t arbiter; /* System Arbiter Registers */
726 reset83xx_t reset; /* Reset Module */
727 clk83xx_t clk; /* System Clock Module */
728 pmc83xx_t pmc; /* Power Management Control Module */
729 gpio83xx_t gpio[1]; /* General purpose I/O module */
731 ddr83xx_t ddr; /* DDR Memory Controller Memory */
732 fsl_i2c_t i2c[2]; /* I2C Controllers */
734 duart83xx_t duart[2]; /* DUART */
736 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
738 spi8xxx_t spi; /* Serial Peripheral Interface */
739 dma83xx_t dma; /* DMA */
740 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
742 ios83xx_t ios; /* Sequencer */
743 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
745 pex83xx_t pciexp[2]; /* PCI Express Controller */
747 tdm83xx_t tdm; /* TDM Controller */
749 sata83xx_t sata[2]; /* SATA Controller */
751 usb83xx_t usb[1]; /* USB DR Controller */
754 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
756 security83xx_t security;
758 serdes83xx_t serdes[1]; /* SerDes Registers */
762 #elif defined(CONFIG_MPC837x)
763 typedef struct immap {
764 sysconf83xx_t sysconf; /* System configuration */
765 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
766 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
767 rtclk83xx_t pit; /* Periodic Interval Timer */
768 gtm83xx_t gtm[2]; /* Global Timers Module */
769 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
770 arbiter83xx_t arbiter; /* System Arbiter Registers */
771 reset83xx_t reset; /* Reset Module */
772 clk83xx_t clk; /* System Clock Module */
773 pmc83xx_t pmc; /* Power Management Control Module */
774 gpio83xx_t gpio[2]; /* General purpose I/O module */
776 ddr83xx_t ddr; /* DDR Memory Controller Memory */
777 fsl_i2c_t i2c[2]; /* I2C Controllers */
779 duart83xx_t duart[2]; /* DUART */
781 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
783 spi8xxx_t spi; /* Serial Peripheral Interface */
784 dma83xx_t dma; /* DMA */
785 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
787 ios83xx_t ios; /* Sequencer */
788 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
790 pex83xx_t pciexp[2]; /* PCI Express Controller */
792 sata83xx_t sata[4]; /* SATA Controller */
794 usb83xx_t usb[1]; /* USB DR Controller */
797 sdhc83xx_t sdhc; /* SDHC Controller */
799 security83xx_t security;
801 serdes83xx_t serdes[2]; /* SerDes Registers */
803 rom83xx_t rom; /* On Chip ROM */
806 #elif defined(CONFIG_MPC8360)
807 typedef struct immap {
808 sysconf83xx_t sysconf; /* System configuration */
809 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
810 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
811 rtclk83xx_t pit; /* Periodic Interval Timer */
813 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
814 arbiter83xx_t arbiter; /* System Arbiter Registers */
815 reset83xx_t reset; /* Reset Module */
816 clk83xx_t clk; /* System Clock Module */
817 pmc83xx_t pmc; /* Power Management Control Module */
818 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
823 qepio83xx_t qepio; /* QE Parallel I/O ports */
824 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
826 ddr83xx_t ddr; /* DDR Memory Controller Memory */
827 fsl_i2c_t i2c[2]; /* I2C Controllers */
829 duart83xx_t duart[2]; /* DUART */
831 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
833 dma83xx_t dma; /* DMA */
834 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
836 ios83xx_t ios; /* Sequencer (IOS) */
837 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
839 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
841 security83xx_t security;
843 u8 qe[0x100000]; /* QE block */
846 #elif defined(CONFIG_MPC832x)
847 typedef struct immap {
848 sysconf83xx_t sysconf; /* System configuration */
849 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
850 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
851 rtclk83xx_t pit; /* Periodic Interval Timer */
852 gtm83xx_t gtm[2]; /* Global Timers Module */
853 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
854 arbiter83xx_t arbiter; /* System Arbiter Registers */
855 reset83xx_t reset; /* Reset Module */
856 clk83xx_t clk; /* System Clock Module */
857 pmc83xx_t pmc; /* Power Management Control Module */
858 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
863 qepio83xx_t qepio; /* QE Parallel I/O ports */
865 ddr83xx_t ddr; /* DDR Memory Controller Memory */
866 fsl_i2c_t i2c[2]; /* I2C Controllers */
868 duart83xx_t duart[2]; /* DUART */
870 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
872 dma83xx_t dma; /* DMA */
873 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
875 ios83xx_t ios; /* Sequencer (IOS) */
876 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
878 security83xx_t security;
880 u8 qe[0x100000]; /* QE block */
882 #elif defined(CONFIG_MPC8309)
883 typedef struct immap {
884 sysconf83xx_t sysconf; /* System configuration */
885 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
886 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
887 rtclk83xx_t pit; /* Periodic Interval Timer */
888 gtm83xx_t gtm[2]; /* Global Timers Module */
889 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
890 arbiter83xx_t arbiter; /* System Arbiter Registers */
891 reset83xx_t reset; /* Reset Module */
892 clk83xx_t clk; /* System Clock Module */
893 pmc83xx_t pmc; /* Power Management Control Module */
894 gpio83xx_t gpio[2]; /* General purpose I/O module */
895 u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
896 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
897 qepio83xx_t qepio; /* QE Parallel I/O ports */
899 ddr83xx_t ddr; /* DDR Memory Controller Memory */
900 fsl_i2c_t i2c[2]; /* I2C Controllers */
902 duart83xx_t duart[2]; /* DUART */
904 duart83xx_t duart1[2]; /* DUART */
906 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
910 dma83xx_t dma; /* DMA */
911 pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
913 ios83xx_t ios; /* Sequencer (IOS) */
914 pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
916 u8 can1[0x1000]; /* Flexcan 1 */
917 u8 can2[0x1000]; /* Flexcan 2 */
921 u8 can3[0x1000]; /* Flexcan 3 */
922 u8 can4[0x1000]; /* Flexcan 4 */
924 u8 dma1[0x2000]; /* DMA */
925 sdhc83xx_t sdhc; /* SDHC Controller */
927 rom83xx_t rom; /* On Chip ROM */
929 u8 qe[0x100000]; /* QE block */
930 u8 res14[0xE00000];/* Added for 8309 */
934 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
935 #define CONFIG_SYS_FSL_DDR_ADDR \
936 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
937 #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
938 #define CONFIG_SYS_MPC83xx_DMA_ADDR \
939 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
940 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
941 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
942 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
944 #ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
945 #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000
947 #define CONFIG_SYS_MPC83xx_USB1_ADDR \
948 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
949 #if defined(CONFIG_MPC834x)
950 #define CONFIG_SYS_MPC83xx_USB2_ADDR \
951 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
953 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
955 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
956 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
958 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
959 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
960 #endif /* __IMMAP_83xx__ */