1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
6 #ifndef __FSL_SECURE_BOOT_H
7 #define __FSL_SECURE_BOOT_H
8 #include <asm/config_mpc85xx.h>
10 #ifdef CONFIG_SECURE_BOOT
11 #if defined(CONFIG_FSL_CORENET)
12 #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
13 #elif defined(CONFIG_TARGET_BSC9132QDS)
14 #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
15 #elif defined(CONFIG_TARGET_C29XPCIE)
16 #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
18 #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
20 #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
22 #if defined(CONFIG_TARGET_B4860QDS) || \
23 defined(CONFIG_TARGET_B4420QDS) || \
24 defined(CONFIG_TARGET_T4160QDS) || \
25 defined(CONFIG_TARGET_T4240QDS) || \
26 defined(CONFIG_TARGET_T2080QDS) || \
27 defined(CONFIG_TARGET_T2080RDB) || \
28 defined(CONFIG_TARGET_T1040QDS) || \
29 defined(CONFIG_TARGET_T1040RDB) || \
30 defined(CONFIG_TARGET_T1040D4RDB) || \
31 defined(CONFIG_TARGET_T1042RDB) || \
32 defined(CONFIG_TARGET_T1042D4RDB) || \
33 defined(CONFIG_TARGET_T1042RDB_PI) || \
34 defined(CONFIG_ARCH_T1023) || \
35 defined(CONFIG_ARCH_T1024)
36 #ifndef CONFIG_SYS_RAMBOOT
37 #define CONFIG_SYS_CPC_REINIT_F
39 #define CONFIG_KEY_REVOCATION
40 #undef CONFIG_SYS_INIT_L3_ADDR
41 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
44 #if defined(CONFIG_RAMBOOT_PBL)
45 #undef CONFIG_SYS_INIT_L3_ADDR
46 #ifdef CONFIG_SYS_INIT_L3_VADDR
47 #define CONFIG_SYS_INIT_L3_ADDR \
48 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
51 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
55 #if defined(CONFIG_TARGET_C29XPCIE)
56 #define CONFIG_KEY_REVOCATION
59 #if defined(CONFIG_ARCH_P3041) || \
60 defined(CONFIG_ARCH_P4080) || \
61 defined(CONFIG_ARCH_P5020) || \
62 defined(CONFIG_ARCH_P5040) || \
63 defined(CONFIG_ARCH_P2041)
64 #define CONFIG_FSL_TRUST_ARCH_v1
67 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
68 /* The key used for verification of next level images
69 * is picked up from an Extension Table which has
70 * been verified by the ISBC (Internal Secure boot Code)
71 * in boot ROM of the SoC.
72 * The feature is only applicable in case of NOR boot and is
73 * not applicable in case of RAMBOOT (NAND, SD, SPI).
75 #define CONFIG_FSL_ISBC_KEY_EXT
77 #endif /* #ifdef CONFIG_SECURE_BOOT */
79 #ifdef CONFIG_CHAIN_OF_TRUST
80 #ifdef CONFIG_SPL_BUILD
82 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
83 * due to space crunch on CPC and thus malloc will not work.
85 #define CONFIG_SPL_PPAACT_ADDR 0x2e000000
86 #define CONFIG_SPL_SPAACT_ADDR 0x2f000000
87 #define CONFIG_SPL_JR0_LIODN_S 454
88 #define CONFIG_SPL_JR0_LIODN_NS 458
90 * Define the key hash for U-Boot here if public/private key pair used to
91 * sign U-boot are different from the SRK hash put in the fuse
92 * Example of defining KEY_HASH is
93 * #define CONFIG_SPL_UBOOT_KEY_HASH \
94 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
95 * else leave it defined as NULL
98 #define CONFIG_SPL_UBOOT_KEY_HASH NULL
99 #endif /* ifdef CONFIG_SPL_BUILD */
101 #define CONFIG_FSL_SEC_MON
103 #ifndef CONFIG_SPL_BUILD
105 * fsl_setenv_chain_of_trust() must be called from
109 /* If Boot Script is not on NOR and is required to be copied on RAM */
110 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
111 #define CONFIG_BS_HDR_ADDR_RAM 0x00010000
112 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
113 #define CONFIG_BS_HDR_SIZE 0x00002000
114 #define CONFIG_BS_ADDR_RAM 0x00012000
115 #define CONFIG_BS_ADDR_DEVICE 0x00802000
116 #define CONFIG_BS_SIZE 0x00001000
118 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
121 /* The bootscript header address is different for B4860 because the NOR
122 * mapping is different on B4 due to reduced NOR size.
124 #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
125 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
126 #elif defined(CONFIG_FSL_CORENET)
127 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
128 #elif defined(CONFIG_TARGET_BSC9132QDS)
129 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
130 #elif defined(CONFIG_TARGET_C29XPCIE)
131 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
133 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
136 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
138 #include <config_fsl_chain_trust.h>
139 #endif /* #ifndef CONFIG_SPL_BUILD */
140 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */