arch/powerpc/include/asm/fsl_lbc.h

   1 /*
   2  * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #ifndef __ASM_PPC_FSL_LBC_H
  14 #define __ASM_PPC_FSL_LBC_H
  15
  16 #include <config.h>
  17 #include <common.h>
  18
  19 /* BR - Base Registers
  20  */
  21 #define BR0                             0x5000          /* Register offset to immr */
  22 #define BR1                             0x5008
  23 #define BR2                             0x5010
  24 #define BR3                             0x5018
  25 #define BR4                             0x5020
  26 #define BR5                             0x5028
  27 #define BR6                             0x5030
  28 #define BR7                             0x5038
  29
  30 #define BR_BA                           0xFFFF8000
  31 #define BR_BA_SHIFT                     15
  32 #define BR_XBA                          0x00006000
  33 #define BR_XBA_SHIFT                    13
  34 #define BR_PS                           0x00001800
  35 #define BR_PS_SHIFT                     11
  36 #define BR_PS_8                         0x00000800      /* Port Size 8 bit */
  37 #define BR_PS_16                        0x00001000      /* Port Size 16 bit */
  38 #define BR_PS_32                        0x00001800      /* Port Size 32 bit */
  39 #define BR_DECC                         0x00000600
  40 #define BR_DECC_SHIFT                   9
  41 #define BR_DECC_OFF                     0x00000000
  42 #define BR_DECC_CHK                     0x00000200
  43 #define BR_DECC_CHK_GEN                 0x00000400
  44 #define BR_WP                           0x00000100
  45 #define BR_WP_SHIFT                     8
  46 #define BR_MSEL                         0x000000E0
  47 #define BR_MSEL_SHIFT                   5
  48 #define BR_MS_GPCM                      0x00000000      /* GPCM */
  49 #define BR_MS_FCM                       0x00000020      /* FCM */
  50 #ifdef CONFIG_MPC83xx
  51 #define BR_MS_SDRAM                     0x00000060      /* SDRAM */
  52 #elif defined(CONFIG_MPC85xx)
  53 #define BR_MS_SDRAM                     0x00000000      /* SDRAM */
  54 #endif
  55 #define BR_MS_UPMA                      0x00000080      /* UPMA */
  56 #define BR_MS_UPMB                      0x000000A0      /* UPMB */
  57 #define BR_MS_UPMC                      0x000000C0      /* UPMC */
  58 #if !defined(CONFIG_MPC834x)
  59 #define BR_ATOM                         0x0000000C
  60 #define BR_ATOM_SHIFT                   2
  61 #endif
  62 #define BR_V                            0x00000001
  63 #define BR_V_SHIFT                      0
  64
  65 #define UPMA                    0
  66 #define UPMB                    1
  67 #define UPMC                    2
  68
  69 #if defined(CONFIG_MPC834x)
  70 #define BR_RES                          ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
  71 #else
  72 #define BR_RES                          ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
  73 #endif
  74
  75 /* Convert an address into the right format for the BR registers */
  76 #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
  77 #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
  78                                          ((x & 0x300000000ULL) >> 19)))
  79 #else
  80 #define BR_PHYS_ADDR(x) (x & 0xffff8000)
  81 #endif
  82
  83 /* OR - Option Registers
  84  */
  85 #define OR0                             0x5004          /* Register offset to immr */
  86 #define OR1                             0x500C
  87 #define OR2                             0x5014
  88 #define OR3                             0x501C
  89 #define OR4                             0x5024
  90 #define OR5                             0x502C
  91 #define OR6                             0x5034
  92 #define OR7                             0x503C
  93
  94 #define OR_GPCM_AM                      0xFFFF8000
  95 #define OR_GPCM_AM_SHIFT                15
  96 #define OR_GPCM_XAM                     0x00006000
  97 #define OR_GPCM_XAM_SHIFT               13
  98 #define OR_GPCM_BCTLD                   0x00001000
  99 #define OR_GPCM_BCTLD_SHIFT             12
 100 #define OR_GPCM_CSNT                    0x00000800
 101 #define OR_GPCM_CSNT_SHIFT              11
 102 #define OR_GPCM_ACS                     0x00000600
 103 #define OR_GPCM_ACS_SHIFT               9
 104 #define OR_GPCM_ACS_DIV2                0x00000600
 105 #define OR_GPCM_ACS_DIV4                0x00000400
 106 #define OR_GPCM_XACS                    0x00000100
 107 #define OR_GPCM_XACS_SHIFT              8
 108 #define OR_GPCM_SCY                     0x000000F0
 109 #define OR_GPCM_SCY_SHIFT               4
 110 #define OR_GPCM_SCY_1                   0x00000010
 111 #define OR_GPCM_SCY_2                   0x00000020
 112 #define OR_GPCM_SCY_3                   0x00000030
 113 #define OR_GPCM_SCY_4                   0x00000040
 114 #define OR_GPCM_SCY_5                   0x00000050
 115 #define OR_GPCM_SCY_6                   0x00000060
 116 #define OR_GPCM_SCY_7                   0x00000070
 117 #define OR_GPCM_SCY_8                   0x00000080
 118 #define OR_GPCM_SCY_9                   0x00000090
 119 #define OR_GPCM_SCY_10                  0x000000a0
 120 #define OR_GPCM_SCY_11                  0x000000b0
 121 #define OR_GPCM_SCY_12                  0x000000c0
 122 #define OR_GPCM_SCY_13                  0x000000d0
 123 #define OR_GPCM_SCY_14                  0x000000e0
 124 #define OR_GPCM_SCY_15                  0x000000f0
 125 #define OR_GPCM_SETA                    0x00000008
 126 #define OR_GPCM_SETA_SHIFT              3
 127 #define OR_GPCM_TRLX                    0x00000004
 128 #define OR_GPCM_TRLX_SHIFT              2
 129 #define OR_GPCM_TRLX_CLEAR              0x00000000
 130 #define OR_GPCM_TRLX_SET                0x00000004
 131 #define OR_GPCM_EHTR                    0x00000002
 132 #define OR_GPCM_EHTR_SHIFT              1
 133 #define OR_GPCM_EHTR_CLEAR              0x00000000
 134 #define OR_GPCM_EHTR_SET                0x00000002
 135 #define OR_GPCM_EAD                     0x00000001
 136 #define OR_GPCM_EAD_SHIFT               0
 137
 138 /* helpers to convert values into an OR address mask (GPCM mode) */
 139 #define P2SZ_TO_AM(s)   ((~((s) - 1)) & 0xffff8000)     /* must be pow of 2 */
 140 #define MEG_TO_AM(m)    P2SZ_TO_AM((m) << 20)
 141
 142 #define OR_FCM_AM                       0xFFFF8000
 143 #define OR_FCM_AM_SHIFT                         15
 144 #define OR_FCM_XAM                      0x00006000
 145 #define OR_FCM_XAM_SHIFT                13
 146 #define OR_FCM_BCTLD                    0x00001000
 147 #define OR_FCM_BCTLD_SHIFT                      12
 148 #define OR_FCM_PGS                      0x00000400
 149 #define OR_FCM_PGS_SHIFT                        10
 150 #define OR_FCM_CSCT                     0x00000200
 151 #define OR_FCM_CSCT_SHIFT                        9
 152 #define OR_FCM_CST                      0x00000100
 153 #define OR_FCM_CST_SHIFT                         8
 154 #define OR_FCM_CHT                      0x00000080
 155 #define OR_FCM_CHT_SHIFT                         7
 156 #define OR_FCM_SCY                      0x00000070
 157 #define OR_FCM_SCY_SHIFT                         4
 158 #define OR_FCM_SCY_1                    0x00000010
 159 #define OR_FCM_SCY_2                    0x00000020
 160 #define OR_FCM_SCY_3                    0x00000030
 161 #define OR_FCM_SCY_4                    0x00000040
 162 #define OR_FCM_SCY_5                    0x00000050
 163 #define OR_FCM_SCY_6                    0x00000060
 164 #define OR_FCM_SCY_7                    0x00000070
 165 #define OR_FCM_RST                      0x00000008
 166 #define OR_FCM_RST_SHIFT                         3
 167 #define OR_FCM_TRLX                     0x00000004
 168 #define OR_FCM_TRLX_SHIFT                        2
 169 #define OR_FCM_EHTR                     0x00000002
 170 #define OR_FCM_EHTR_SHIFT                        1
 171
 172 #define OR_UPM_AM                       0xFFFF8000
 173 #define OR_UPM_AM_SHIFT                 15
 174 #define OR_UPM_XAM                      0x00006000
 175 #define OR_UPM_XAM_SHIFT                13
 176 #define OR_UPM_BCTLD                    0x00001000
 177 #define OR_UPM_BCTLD_SHIFT              12
 178 #define OR_UPM_BI                       0x00000100
 179 #define OR_UPM_BI_SHIFT                 8
 180 #define OR_UPM_TRLX                     0x00000004
 181 #define OR_UPM_TRLX_SHIFT               2
 182 #define OR_UPM_EHTR                     0x00000002
 183 #define OR_UPM_EHTR_SHIFT               1
 184 #define OR_UPM_EAD                      0x00000001
 185 #define OR_UPM_EAD_SHIFT                0
 186
 187 #define OR_SDRAM_AM                     0xFFFF8000
 188 #define OR_SDRAM_AM_SHIFT               15
 189 #define OR_SDRAM_XAM                    0x00006000
 190 #define OR_SDRAM_XAM_SHIFT              13
 191 #define OR_SDRAM_COLS                   0x00001C00
 192 #define OR_SDRAM_COLS_SHIFT             10
 193 #define OR_SDRAM_ROWS                   0x000001C0
 194 #define OR_SDRAM_ROWS_SHIFT             6
 195 #define OR_SDRAM_PMSEL                  0x00000020
 196 #define OR_SDRAM_PMSEL_SHIFT            5
 197 #define OR_SDRAM_EAD                    0x00000001
 198 #define OR_SDRAM_EAD_SHIFT              0
 199
 200 #define OR_AM_32KB                      0xFFFF8000
 201 #define OR_AM_64KB                      0xFFFF0000
 202 #define OR_AM_128KB                     0xFFFE0000
 203 #define OR_AM_256KB                     0xFFFC0000
 204 #define OR_AM_512KB                     0xFFF80000
 205 #define OR_AM_1MB                       0xFFF00000
 206 #define OR_AM_2MB                       0xFFE00000
 207 #define OR_AM_4MB                       0xFFC00000
 208 #define OR_AM_8MB                       0xFF800000
 209 #define OR_AM_16MB                      0xFF000000
 210 #define OR_AM_32MB                      0xFE000000
 211 #define OR_AM_64MB                      0xFC000000
 212 #define OR_AM_128MB                     0xF8000000
 213 #define OR_AM_256MB                     0xF0000000
 214 #define OR_AM_512MB                     0xE0000000
 215 #define OR_AM_1GB                       0xC0000000
 216 #define OR_AM_2GB                       0x80000000
 217 #define OR_AM_4GB                       0x00000000
 218
 219 /* MxMR - UPM Machine A/B/C Mode Registers
 220  */
 221 #define MxMR_MAD_MSK            0x0000003f /* Machine Address Mask         */
 222 #define MxMR_TLFx_MSK           0x000003c0 /* Refresh Loop Field Mask      */
 223 #define MxMR_WLFx_MSK           0x00003c00 /* Write Loop Field Mask        */
 224 #define MxMR_WLFx_1X            0x00000400 /*   executed 1 time            */
 225 #define MxMR_WLFx_2X            0x00000800 /*   executed 2 times           */
 226 #define MxMR_WLFx_3X            0x00000c00 /*   executed 3 times           */
 227 #define MxMR_WLFx_4X            0x00001000 /*   executed 4 times           */
 228 #define MxMR_WLFx_5X            0x00001400 /*   executed 5 times           */
 229 #define MxMR_WLFx_6X            0x00001800 /*   executed 6 times           */
 230 #define MxMR_WLFx_7X            0x00001c00 /*   executed 7 times           */
 231 #define MxMR_WLFx_8X            0x00002000 /*   executed 8 times           */
 232 #define MxMR_WLFx_9X            0x00002400 /*   executed 9 times           */
 233 #define MxMR_WLFx_10X           0x00002800 /*   executed 10 times          */
 234 #define MxMR_WLFx_11X           0x00002c00 /*   executed 11 times          */
 235 #define MxMR_WLFx_12X           0x00003000 /*   executed 12 times          */
 236 #define MxMR_WLFx_13X           0x00003400 /*   executed 13 times          */
 237 #define MxMR_WLFx_14X           0x00003800 /*   executed 14 times          */
 238 #define MxMR_WLFx_15X           0x00003c00 /*   executed 15 times          */
 239 #define MxMR_WLFx_16X           0x00000000 /*   executed 16 times          */
 240 #define MxMR_RLFx_MSK           0x0003c000 /* Read Loop Field Mask         */
 241 #define MxMR_GPL_x4DIS          0x00040000 /* GPL_A4 Ouput Line Disable    */
 242 #define MxMR_G0CLx_MSK          0x00380000 /* General Line 0 Control Mask  */
 243 #define MxMR_DSx_1_CYCL         0x00000000 /* 1 cycle Disable Period       */
 244 #define MxMR_DSx_2_CYCL         0x00400000 /* 2 cycle Disable Period       */
 245 #define MxMR_DSx_3_CYCL         0x00800000 /* 3 cycle Disable Period       */
 246 #define MxMR_DSx_4_CYCL         0x00c00000 /* 4 cycle Disable Period       */
 247 #define MxMR_DSx_MSK            0x00c00000 /* Disable Timer Period Mask    */
 248 #define MxMR_AMx_MSK            0x07000000 /* Addess Multiplex Size Mask   */
 249 #define MxMR_UWPL               0x08000000 /* LUPWAIT Polarity Mask        */
 250 #define MxMR_OP_NORM            0x00000000 /* Normal Operation             */
 251 #define MxMR_OP_WARR            0x10000000 /* Write to Array               */
 252 #define MxMR_OP_RARR            0x20000000 /* Read from Array              */
 253 #define MxMR_OP_RUNP            0x30000000 /* Run Pattern                  */
 254 #define MxMR_OP_MSK             0x30000000 /* Command Opcode Mask          */
 255 #define MxMR_RFEN               0x40000000 /* Refresh Enable               */
 256 #define MxMR_BSEL               0x80000000 /* Bus Select                   */
 257
 258 #define LBLAWAR_EN                      0x80000000
 259 #define LBLAWAR_4KB                     0x0000000B
 260 #define LBLAWAR_8KB                     0x0000000C
 261 #define LBLAWAR_16KB                    0x0000000D
 262 #define LBLAWAR_32KB                    0x0000000E
 263 #define LBLAWAR_64KB                    0x0000000F
 264 #define LBLAWAR_128KB                   0x00000010
 265 #define LBLAWAR_256KB                   0x00000011
 266 #define LBLAWAR_512KB                   0x00000012
 267 #define LBLAWAR_1MB                     0x00000013
 268 #define LBLAWAR_2MB                     0x00000014
 269 #define LBLAWAR_4MB                     0x00000015
 270 #define LBLAWAR_8MB                     0x00000016
 271 #define LBLAWAR_16MB                    0x00000017
 272 #define LBLAWAR_32MB                    0x00000018
 273 #define LBLAWAR_64MB                    0x00000019
 274 #define LBLAWAR_128MB                   0x0000001A
 275 #define LBLAWAR_256MB                   0x0000001B
 276 #define LBLAWAR_512MB                   0x0000001C
 277 #define LBLAWAR_1GB                     0x0000001D
 278 #define LBLAWAR_2GB                     0x0000001E
 279
 280 /* LBCR - Local Bus Configuration Register
 281  */
 282 #define LBCR_LDIS                       0x80000000
 283 #define LBCR_LDIS_SHIFT                 31
 284 #define LBCR_BCTLC                      0x00C00000
 285 #define LBCR_BCTLC_SHIFT                22
 286 #define LBCR_LPBSE                      0x00020000
 287 #define LBCR_LPBSE_SHIFT                17
 288 #define LBCR_EPAR                       0x00010000
 289 #define LBCR_EPAR_SHIFT                 16
 290 #define LBCR_BMT                        0x0000FF00
 291 #define LBCR_BMT_SHIFT                  8
 292
 293 /* LCRR - Clock Ratio Register
 294  */
 295 #define LCRR_DBYP                       0x80000000
 296 #define LCRR_DBYP_SHIFT                 31
 297 #define LCRR_BUFCMDC                    0x30000000
 298 #define LCRR_BUFCMDC_SHIFT              28
 299 #define LCRR_BUFCMDC_1                  0x10000000
 300 #define LCRR_BUFCMDC_2                  0x20000000
 301 #define LCRR_BUFCMDC_3                  0x30000000
 302 #define LCRR_BUFCMDC_4                  0x00000000
 303 #define LCRR_ECL                        0x03000000
 304 #define LCRR_ECL_SHIFT                  24
 305 #define LCRR_ECL_4                      0x00000000
 306 #define LCRR_ECL_5                      0x01000000
 307 #define LCRR_ECL_6                      0x02000000
 308 #define LCRR_ECL_7                      0x03000000
 309 #define LCRR_EADC                       0x00030000
 310 #define LCRR_EADC_SHIFT                 16
 311 #define LCRR_EADC_1                     0x00010000
 312 #define LCRR_EADC_2                     0x00020000
 313 #define LCRR_EADC_3                     0x00030000
 314 #define LCRR_EADC_4                     0x00000000
 315 /* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
 316  * should always be zero on older parts that have a four bit CLKDIV.
 317  */
 318 #define LCRR_CLKDIV                     0x0000001F
 319 #define LCRR_CLKDIV_SHIFT               0
 320 #if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
 321     defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
 322     defined(CONFIG_MPC8560)
 323 #define LCRR_CLKDIV_2                   0x00000002
 324 #define LCRR_CLKDIV_4                   0x00000004
 325 #define LCRR_CLKDIV_8                   0x00000008
 326 #elif defined(CONFIG_FSL_CORENET)
 327 #define LCRR_CLKDIV_8                   0x00000002
 328 #define LCRR_CLKDIV_16                  0x00000004
 329 #define LCRR_CLKDIV_32                  0x00000008
 330 #else
 331 #define LCRR_CLKDIV_4                   0x00000002
 332 #define LCRR_CLKDIV_8                   0x00000004
 333 #define LCRR_CLKDIV_16                  0x00000008
 334 #endif
 335
 336 /* LTEDR - Transfer Error Check Disable Register
 337  */
 338 #define LTEDR_BMD       0x80000000 /* Bus monitor disable                               */
 339 #define LTEDR_PARD      0x20000000 /* Parity error checking disabled                    */
 340 #define LTEDR_WPD       0x04000000 /* Write protect error checking diable               */
 341 #define LTEDR_WARA      0x00800000 /* Write-after-read-atomic error checking diable     */
 342 #define LTEDR_RAWA      0x00400000 /* Read-after-write-atomic error checking disable    */
 343 #define LTEDR_CSD       0x00080000 /* Chip select error checking disable                */
 344
 345 /* FMR - Flash Mode Register
 346  */
 347 #define FMR_CWTO               0x0000F000
 348 #define FMR_CWTO_SHIFT         12
 349 #define FMR_BOOT               0x00000800
 350 #define FMR_ECCM               0x00000100
 351 #define FMR_AL                 0x00000030
 352 #define FMR_AL_SHIFT           4
 353 #define FMR_OP                 0x00000003
 354 #define FMR_OP_SHIFT           0
 355
 356 /* FIR - Flash Instruction Register
 357  */
 358 #define FIR_OP0                        0xF0000000
 359 #define FIR_OP0_SHIFT          28
 360 #define FIR_OP1                        0x0F000000
 361 #define FIR_OP1_SHIFT          24
 362 #define FIR_OP2                        0x00F00000
 363 #define FIR_OP2_SHIFT          20
 364 #define FIR_OP3                        0x000F0000
 365 #define FIR_OP3_SHIFT          16
 366 #define FIR_OP4                        0x0000F000
 367 #define FIR_OP4_SHIFT          12
 368 #define FIR_OP5                        0x00000F00
 369 #define FIR_OP5_SHIFT          8
 370 #define FIR_OP6                        0x000000F0
 371 #define FIR_OP6_SHIFT          4
 372 #define FIR_OP7                        0x0000000F
 373 #define FIR_OP7_SHIFT          0
 374 #define FIR_OP_NOP             0x0 /* No operation and end of sequence */
 375 #define FIR_OP_CA              0x1 /* Issue current column address */
 376 #define FIR_OP_PA              0x2 /* Issue current block+page address */
 377 #define FIR_OP_UA              0x3 /* Issue user defined address */
 378 #define FIR_OP_CM0             0x4 /* Issue command from FCR[CMD0] */
 379 #define FIR_OP_CM1             0x5 /* Issue command from FCR[CMD1] */
 380 #define FIR_OP_CM2             0x6 /* Issue command from FCR[CMD2] */
 381 #define FIR_OP_CM3             0x7 /* Issue command from FCR[CMD3] */
 382 #define FIR_OP_WB              0x8 /* Write FBCR bytes from FCM buffer */
 383 #define FIR_OP_WS              0x9 /* Write 1 or 2 bytes from MDR[AS] */
 384 #define FIR_OP_RB              0xA /* Read FBCR bytes to FCM buffer */
 385 #define FIR_OP_RS              0xB /* Read 1 or 2 bytes to MDR[AS] */
 386 #define FIR_OP_CW0             0xC /* Wait then issue FCR[CMD0] */
 387 #define FIR_OP_CW1             0xD /* Wait then issue FCR[CMD1] */
 388 #define FIR_OP_RBW             0xE /* Wait then read FBCR bytes */
 389 #define FIR_OP_RSW             0xF /* Wait then read 1 or 2 bytes */
 390
 391 /* FCR - Flash Command Register
 392  */
 393 #define FCR_CMD0               0xFF000000
 394 #define FCR_CMD0_SHIFT         24
 395 #define FCR_CMD1               0x00FF0000
 396 #define FCR_CMD1_SHIFT         16
 397 #define FCR_CMD2               0x0000FF00
 398 #define FCR_CMD2_SHIFT         8
 399 #define FCR_CMD3               0x000000FF
 400 #define FCR_CMD3_SHIFT         0
 401 /* FBAR - Flash Block Address Register
 402  */
 403 #define FBAR_BLK               0x00FFFFFF
 404
 405 /* FPAR - Flash Page Address Register
 406  */
 407 #define FPAR_SP_PI             0x00007C00
 408 #define FPAR_SP_PI_SHIFT       10
 409 #define FPAR_SP_MS             0x00000200
 410 #define FPAR_SP_CI             0x000001FF
 411 #define FPAR_SP_CI_SHIFT       0
 412 #define FPAR_LP_PI             0x0003F000
 413 #define FPAR_LP_PI_SHIFT       12
 414 #define FPAR_LP_MS             0x00000800
 415 #define FPAR_LP_CI             0x000007FF
 416 #define FPAR_LP_CI_SHIFT       0
 417
 418 /* LSDMR - SDRAM Machine Mode Register
 419  */
 420 #define LSDMR_RFEN      (1 << (31 -  1))
 421 #define LSDMR_BSMA1516  (3 << (31 - 10))
 422 #define LSDMR_BSMA1617  (4 << (31 - 10))
 423 #define LSDMR_RFCR5     (3 << (31 - 16))
 424 #define LSDMR_RFCR16    (7 << (31 - 16))
 425 #define LSDMR_PRETOACT3 (3 << (31 - 19))
 426 #define LSDMR_PRETOACT7 (7 << (31 - 19))
 427 #define LSDMR_ACTTORW3  (3 << (31 - 22))
 428 #define LSDMR_ACTTORW7  (7 << (31 - 22))
 429 #define LSDMR_ACTTORW6  (6 << (31 - 22))
 430 #define LSDMR_BL8       (1 << (31 - 23))
 431 #define LSDMR_WRC2      (2 << (31 - 27))
 432 #define LSDMR_WRC4      (0 << (31 - 27))
 433 #define LSDMR_BUFCMD    (1 << (31 - 29))
 434 #define LSDMR_CL3       (3 << (31 - 31))
 435
 436 #define LSDMR_OP_NORMAL (0 << (31 - 4))
 437 #define LSDMR_OP_ARFRSH (1 << (31 - 4))
 438 #define LSDMR_OP_SRFRSH (2 << (31 - 4))
 439 #define LSDMR_OP_MRW    (3 << (31 - 4))
 440 #define LSDMR_OP_PRECH  (4 << (31 - 4))
 441 #define LSDMR_OP_PCHALL (5 << (31 - 4))
 442 #define LSDMR_OP_ACTBNK (6 << (31 - 4))
 443 #define LSDMR_OP_RWINV  (7 << (31 - 4))
 444
 445 /* LTESR - Transfer Error Status Register
 446  */
 447 #define LTESR_BM               0x80000000
 448 #define LTESR_FCT              0x40000000
 449 #define LTESR_PAR              0x20000000
 450 #define LTESR_WP               0x04000000
 451 #define LTESR_ATMW             0x00800000
 452 #define LTESR_ATMR             0x00400000
 453 #define LTESR_CS               0x00080000
 454 #define LTESR_CC               0x00000001
 455
 456 #ifndef __ASSEMBLY__
 457 #include <asm/io.h>
 458
 459 extern void print_lbc_regs(void);
 460 extern void init_early_memctl_regs(void);
 461
 462 #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
 463 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
 464 #define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
 465 #define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
 466 #define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
 467
 468 typedef struct lbc_bank {
 469         u32     br;
 470         u32     or;
 471 } lbc_bank_t;
 472
 473 /* Local Bus Controller Registers */
 474 typedef struct fsl_lbc {
 475         lbc_bank_t      bank[8];
 476         u8      res1[40];
 477         u32     mar;            /* LBC UPM Addr */
 478         u8      res2[4];
 479         u32     mamr;           /* LBC UPMA Mode */
 480         u32     mbmr;           /* LBC UPMB Mode */
 481         u32     mcmr;           /* LBC UPMC Mode */
 482         u8      res3[8];
 483         u32     mrtpr;          /* LBC Memory Refresh Timer Prescaler */
 484         u32     mdr;            /* LBC UPM Data */
 485 #ifdef CONFIG_FSL_ELBC
 486         u8      res4[4];
 487         u32     lsor;
 488         u8      res5[12];
 489         u32     lurt;           /* LBC UPM Refresh Timer */
 490         u8      res6[4];
 491 #else
 492         u8      res4[8];
 493         u32     lsdmr;          /* LBC SDRAM Mode */
 494         u8      res5[8];
 495         u32     lurt;           /* LBC UPM Refresh Timer */
 496         u32     lsrt;           /* LBC SDRAM Refresh Timer */
 497 #endif
 498         u8      res7[8];
 499         u32     ltesr;          /* LBC Transfer Error Status */
 500         u32     ltedr;          /* LBC Transfer Error Disable */
 501         u32     lteir;          /* LBC Transfer Error IRQ */
 502         u32     lteatr;         /* LBC Transfer Error Attrs */
 503         u32     ltear;          /* LBC Transfer Error Addr */
 504         u8      res8[12];
 505         u32     lbcr;           /* LBC Configuration */
 506         u32     lcrr;           /* LBC Clock Ratio */
 507 #ifdef CONFIG_NAND_FSL_ELBC
 508         u8      res9[0x8];
 509         u32     fmr;            /* Flash Mode Register */
 510         u32     fir;            /* Flash Instruction Register */
 511         u32     fcr;            /* Flash Command Register */
 512         u32     fbar;           /* Flash Block Addr Register */
 513         u32     fpar;           /* Flash Page Addr Register */
 514         u32     fbcr;           /* Flash Byte Count Register */
 515         u8      res10[0xF08];
 516 #else
 517         u8      res9[0xF28];
 518 #endif
 519 } fsl_lbc_t;
 520
 521 #endif /* __ASSEMBLY__ */
 522 #endif /* __ASM_PPC_FSL_LBC_H */