1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Freescale I2C Controller
5 * Copyright 2006 Freescale Semiconductor, Inc.
7 * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
8 * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
10 * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
13 #ifndef _ASM_FSL_I2C_H_
14 #define _ASM_FSL_I2C_H_
16 #include <asm/types.h>
18 typedef struct fsl_i2c_base {
20 u8 adr; /* I2C slave address */
23 #define I2C_ADR_SHIFT 1
24 #define I2C_ADR_RES ~(I2C_ADR)
26 u8 fdr; /* I2C frequency divider register */
29 #define IC2_FDR_SHIFT 0
30 #define IC2_FDR_RES ~(IC2_FDR)
32 u8 cr; /* I2C control redister */
34 #define I2C_CR_MEN 0x80
35 #define I2C_CR_MIEN 0x40
36 #define I2C_CR_MSTA 0x20
37 #define I2C_CR_MTX 0x10
38 #define I2C_CR_TXAK 0x08
39 #define I2C_CR_RSTA 0x04
40 #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */
41 #define I2C_CR_BCST 0x01
43 u8 sr; /* I2C status register */
45 #define I2C_SR_MCF 0x80
46 #define I2C_SR_MAAS 0x40
47 #define I2C_SR_MBB 0x20
48 #define I2C_SR_MAL 0x10
49 #define I2C_SR_BCSTM 0x08
50 #define I2C_SR_SRW 0x04
51 #define I2C_SR_MIF 0x02
52 #define I2C_SR_RXAK 0x01
54 u8 dr; /* I2C data register */
57 #define I2C_DR_SHIFT 0
58 #define I2C_DR_RES ~(I2C_DR)
60 u8 dfsrr; /* I2C digital filter sampling rate register */
62 #define I2C_DFSRR 0x3F
63 #define I2C_DFSRR_SHIFT 0
64 #define I2C_DFSRR_RES ~(I2C_DR)
66 /* Fill out the reserved block */
72 struct fsl_i2c_base __iomem *base; /* register base */
80 #endif /* _ASM_I2C_H_ */