2 * Freescale I2C Controller
4 * Copyright 2006 Freescale Semiconductor, Inc.
6 * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
7 * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
9 * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
11 * This software may be used and distributed according to the
12 * terms of the GNU Public License, Version 2, incorporated
13 * herein by reference.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * Version 2 as published by the Free Software Foundation.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #ifndef _ASM_FSL_I2C_H_
31 #define _ASM_FSL_I2C_H_
33 #include <asm/types.h>
35 typedef struct fsl_i2c {
37 u8 adr; /* I2C slave address */
40 #define I2C_ADR_SHIFT 1
41 #define I2C_ADR_RES ~(I2C_ADR)
43 u8 fdr; /* I2C frequency divider register */
46 #define IC2_FDR_SHIFT 0
47 #define IC2_FDR_RES ~(IC2_FDR)
49 u8 cr; /* I2C control redister */
51 #define I2C_CR_MEN 0x80
52 #define I2C_CR_MIEN 0x40
53 #define I2C_CR_MSTA 0x20
54 #define I2C_CR_MTX 0x10
55 #define I2C_CR_TXAK 0x08
56 #define I2C_CR_RSTA 0x04
57 #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */
58 #define I2C_CR_BCST 0x01
60 u8 sr; /* I2C status register */
62 #define I2C_SR_MCF 0x80
63 #define I2C_SR_MAAS 0x40
64 #define I2C_SR_MBB 0x20
65 #define I2C_SR_MAL 0x10
66 #define I2C_SR_BCSTM 0x08
67 #define I2C_SR_SRW 0x04
68 #define I2C_SR_MIF 0x02
69 #define I2C_SR_RXAK 0x01
71 u8 dr; /* I2C data register */
74 #define I2C_DR_SHIFT 0
75 #define I2C_DR_RES ~(I2C_DR)
77 u8 dfsrr; /* I2C digital filter sampling rate register */
79 #define I2C_DFSRR 0x3F
80 #define I2C_DFSRR_SHIFT 0
81 #define I2C_DFSRR_RES ~(I2C_DR)
83 /* Fill out the reserved block */
87 #endif /* _ASM_I2C_H_ */