2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
13 * This macro should be removed when we no longer care about backwards
14 * compatibility with older operating systems.
16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
18 #include <fsl_ddrc_version.h>
21 #define CONFIG_SYS_FSL_IFC_BE
22 #define CONFIG_SYS_FSL_SFP_BE
23 #define CONFIG_SYS_FSL_SEC_MON_BE
25 #if defined(CONFIG_ARCH_MPC8548)
26 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
27 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
28 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
29 #define CONFIG_SYS_FSL_RMU
30 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
32 #elif defined(CONFIG_ARCH_MPC8568)
33 #define QE_MURAM_SIZE 0x10000UL
35 #define QE_NUM_OF_SNUM 28
36 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
37 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
38 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
39 #define CONFIG_SYS_FSL_RMU
40 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
42 #elif defined(CONFIG_ARCH_MPC8569)
43 #define QE_MURAM_SIZE 0x20000UL
45 #define QE_NUM_OF_SNUM 46
46 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
47 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
48 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
49 #define CONFIG_SYS_FSL_RMU
50 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
52 #elif defined(CONFIG_ARCH_P1010)
53 #define CONFIG_FSL_SDHC_V2_3
55 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
56 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
57 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
58 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
59 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
60 #define CONFIG_ESDHC_HC_BLK_ADDR
62 /* P1011 is single core version of P1020 */
63 #elif defined(CONFIG_ARCH_P1011)
65 #define CONFIG_FSL_PCIE_DISABLE_ASPM
66 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
68 #elif defined(CONFIG_ARCH_P1020)
70 #define CONFIG_FSL_PCIE_DISABLE_ASPM
71 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
72 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
75 #elif defined(CONFIG_ARCH_P1021)
77 #define CONFIG_FSL_PCIE_DISABLE_ASPM
78 #define QE_MURAM_SIZE 0x6000UL
80 #define QE_NUM_OF_SNUM 28
81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
83 #elif defined(CONFIG_ARCH_P1022)
85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
87 #elif defined(CONFIG_ARCH_P1023)
88 #define CONFIG_SYS_NUM_FMAN 1
89 #define CONFIG_SYS_NUM_FM1_DTSEC 2
90 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
91 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
92 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
93 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
94 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
96 /* P1024 is lower end variant of P1020 */
97 #elif defined(CONFIG_ARCH_P1024)
99 #define CONFIG_FSL_PCIE_DISABLE_ASPM
100 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
102 /* P1025 is lower end variant of P1021 */
103 #elif defined(CONFIG_ARCH_P1025)
104 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
105 #define CONFIG_TSECV2
106 #define CONFIG_FSL_PCIE_DISABLE_ASPM
107 #define QE_MURAM_SIZE 0x6000UL
108 #define MAX_QE_RISC 1
109 #define QE_NUM_OF_SNUM 28
111 #elif defined(CONFIG_ARCH_P2020)
112 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
113 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
114 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
115 #define CONFIG_SYS_FSL_RMU
116 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
117 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
119 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
120 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
121 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
122 #define CONFIG_SYS_NUM_FMAN 1
123 #define CONFIG_SYS_NUM_FM1_DTSEC 5
124 #define CONFIG_SYS_NUM_FM1_10GEC 1
125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
126 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
127 #define CONFIG_SYS_FSL_TBCLK_DIV 32
128 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
129 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
130 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
131 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
132 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
133 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
134 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
135 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
137 #elif defined(CONFIG_ARCH_P3041)
138 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
139 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
140 #define CONFIG_SYS_NUM_FMAN 1
141 #define CONFIG_SYS_NUM_FM1_DTSEC 5
142 #define CONFIG_SYS_NUM_FM1_10GEC 1
143 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
144 #define CONFIG_SYS_FSL_TBCLK_DIV 32
145 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
146 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
147 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
148 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
149 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
150 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
151 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
152 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
153 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
155 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
156 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
157 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
158 #define CONFIG_SYS_NUM_FMAN 2
159 #define CONFIG_SYS_NUM_FM1_DTSEC 4
160 #define CONFIG_SYS_NUM_FM2_DTSEC 4
161 #define CONFIG_SYS_NUM_FM1_10GEC 1
162 #define CONFIG_SYS_NUM_FM2_10GEC 1
163 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
164 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
165 #define CONFIG_SYS_FSL_TBCLK_DIV 16
166 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
167 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
168 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
169 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
170 #define CONFIG_SYS_FSL_RMU
171 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
172 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
174 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
175 #define CONFIG_SYS_PPC64 /* 64-bit core */
176 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
177 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
178 #define CONFIG_SYS_NUM_FMAN 1
179 #define CONFIG_SYS_NUM_FM1_DTSEC 5
180 #define CONFIG_SYS_NUM_FM1_10GEC 1
181 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
182 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
183 #define CONFIG_SYS_FSL_TBCLK_DIV 32
184 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
185 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
186 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
187 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
188 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
189 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
190 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
191 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
193 #elif defined(CONFIG_ARCH_P5040)
194 #define CONFIG_SYS_PPC64
195 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
196 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
197 #define CONFIG_SYS_NUM_FMAN 2
198 #define CONFIG_SYS_NUM_FM1_DTSEC 5
199 #define CONFIG_SYS_NUM_FM1_10GEC 1
200 #define CONFIG_SYS_NUM_FM2_DTSEC 5
201 #define CONFIG_SYS_NUM_FM2_10GEC 1
202 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
203 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
204 #define CONFIG_SYS_FSL_TBCLK_DIV 16
205 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
206 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
207 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
208 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
209 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
211 #elif defined(CONFIG_ARCH_BSC9131)
212 #define CONFIG_FSL_SDHC_V2_3
213 #define CONFIG_TSECV2
214 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
215 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
216 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
217 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
218 #define CONFIG_NAND_FSL_IFC
219 #define CONFIG_ESDHC_HC_BLK_ADDR
221 #elif defined(CONFIG_ARCH_BSC9132)
222 #define CONFIG_FSL_SDHC_V2_3
223 #define CONFIG_TSECV2
224 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
225 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
226 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
227 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
228 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
229 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
230 #define CONFIG_NAND_FSL_IFC
231 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
232 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
233 #define CONFIG_ESDHC_HC_BLK_ADDR
235 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
236 #define CONFIG_SYS_PPC64 /* 64-bit core */
237 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
238 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
239 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
240 #ifdef CONFIG_ARCH_T4240
241 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
242 #define CONFIG_SYS_NUM_FM1_DTSEC 8
243 #define CONFIG_SYS_NUM_FM1_10GEC 2
244 #define CONFIG_SYS_NUM_FM2_DTSEC 8
245 #define CONFIG_SYS_NUM_FM2_10GEC 2
247 #define CONFIG_SYS_NUM_FM1_DTSEC 6
248 #define CONFIG_SYS_NUM_FM1_10GEC 1
249 #define CONFIG_SYS_NUM_FM2_DTSEC 8
250 #define CONFIG_SYS_NUM_FM2_10GEC 1
251 #if defined(CONFIG_ARCH_T4160)
252 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
255 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
256 #define CONFIG_SYS_FSL_SRDS_1
257 #define CONFIG_SYS_FSL_SRDS_2
258 #define CONFIG_SYS_FSL_SRDS_3
259 #define CONFIG_SYS_FSL_SRDS_4
260 #define CONFIG_SYS_NUM_FMAN 2
261 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
262 #define CONFIG_SYS_PME_CLK 0
263 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
264 #define CONFIG_SYS_FMAN_V3
265 #define CONFIG_SYS_FM1_CLK 3
266 #define CONFIG_SYS_FM2_CLK 3
267 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
268 #define CONFIG_SYS_FSL_TBCLK_DIV 16
269 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
270 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
271 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
272 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
273 #define CONFIG_SYS_FSL_SRIO_LIODN
274 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
275 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
276 #define CONFIG_SYS_FSL_SFP_VER_3_0
277 #define CONFIG_SYS_FSL_PCI_VER_3_X
279 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
280 #define CONFIG_SYS_PPC64 /* 64-bit core */
281 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
282 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
283 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
284 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
285 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
286 #define CONFIG_SYS_FSL_SRDS_1
287 #define CONFIG_SYS_FSL_SRDS_2
288 #define CONFIG_SYS_MAPLE
289 #define CONFIG_SYS_CPRI
290 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
291 #define CONFIG_SYS_NUM_FMAN 1
292 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
293 #define CONFIG_SYS_FM1_CLK 0
294 #define CONFIG_SYS_CPRI_CLK 3
295 #define CONFIG_SYS_ULB_CLK 4
296 #define CONFIG_SYS_ETVPE_CLK 1
297 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
298 #define CONFIG_SYS_FMAN_V3
299 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
300 #define CONFIG_SYS_FSL_TBCLK_DIV 16
301 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
302 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
303 #define CONFIG_SYS_FSL_SFP_VER_3_0
305 #ifdef CONFIG_ARCH_B4860
306 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
307 #define CONFIG_MAX_DSP_CPUS 12
308 #define CONFIG_NUM_DSP_CPUS 6
309 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
310 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
311 #define CONFIG_SYS_NUM_FM1_DTSEC 6
312 #define CONFIG_SYS_NUM_FM1_10GEC 2
313 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
314 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
315 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
316 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
317 #define CONFIG_SYS_FSL_SRIO_LIODN
319 #define CONFIG_MAX_DSP_CPUS 2
320 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
321 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
322 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
323 #define CONFIG_SYS_NUM_FM1_DTSEC 4
324 #define CONFIG_SYS_NUM_FM1_10GEC 0
327 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
329 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
330 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
331 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
332 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
333 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
334 #define CONFIG_SYS_FSL_SRDS_1
335 #define CONFIG_SYS_NUM_FMAN 1
336 #define CONFIG_SYS_NUM_FM1_DTSEC 5
337 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
338 #define CONFIG_PME_PLAT_CLK_DIV 2
339 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
340 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
341 #define CONFIG_SYS_FMAN_V3
342 #define CONFIG_FM_PLAT_CLK_DIV 1
343 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
344 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
345 per rcw field value */
346 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
347 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
348 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
349 #define CONFIG_SYS_FSL_TBCLK_DIV 16
350 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
351 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
352 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
353 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
354 #define QE_MURAM_SIZE 0x6000UL
355 #define MAX_QE_RISC 1
356 #define QE_NUM_OF_SNUM 28
357 #define CONFIG_SYS_FSL_SFP_VER_3_0
359 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
361 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
362 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
363 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
364 #define CONFIG_SYS_FMAN_V3
365 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
366 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
367 #define CONFIG_SYS_FSL_SRDS_1
368 #define CONFIG_SYS_NUM_FMAN 1
369 #define CONFIG_SYS_NUM_FM1_DTSEC 4
370 #define CONFIG_SYS_NUM_FM1_10GEC 1
371 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
372 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
373 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
374 #define CONFIG_SYS_FM1_CLK 0
375 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
376 per rcw field value */
377 #define CONFIG_QBMAN_CLK_DIV 1
378 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
379 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
380 #define CONFIG_SYS_FSL_TBCLK_DIV 16
381 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
382 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
383 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
384 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
385 #define QE_MURAM_SIZE 0x6000UL
386 #define MAX_QE_RISC 1
387 #define QE_NUM_OF_SNUM 28
388 #define CONFIG_SYS_FSL_SFP_VER_3_0
390 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
391 #define CONFIG_SYS_PPC64 /* 64-bit core */
392 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
393 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
394 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
395 #define CONFIG_SYS_FSL_QMAN_V3
396 #define CONFIG_SYS_NUM_FMAN 1
397 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
398 #define CONFIG_SYS_FSL_SRDS_1
399 #define CONFIG_SYS_FSL_PCI_VER_3_X
400 #if defined(CONFIG_ARCH_T2080)
401 #define CONFIG_SYS_NUM_FM1_DTSEC 8
402 #define CONFIG_SYS_NUM_FM1_10GEC 4
403 #define CONFIG_SYS_FSL_SRDS_2
404 #define CONFIG_SYS_FSL_SRIO_LIODN
405 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
406 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
407 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
408 #elif defined(CONFIG_ARCH_T2081)
409 #define CONFIG_SYS_NUM_FM1_DTSEC 6
410 #define CONFIG_SYS_NUM_FM1_10GEC 2
412 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
413 #define CONFIG_PME_PLAT_CLK_DIV 1
414 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
415 #define CONFIG_SYS_FM1_CLK 0
416 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
417 per rcw field value */
418 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
419 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
420 #define CONFIG_SYS_FMAN_V3
421 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
422 #define CONFIG_SYS_FSL_TBCLK_DIV 16
423 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
424 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
425 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
426 #define CONFIG_SYS_FSL_SFP_VER_3_0
427 #define CONFIG_SYS_FSL_ISBC_VER 2
428 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
429 #define CONFIG_SYS_FSL_SFP_VER_3_0
432 #elif defined(CONFIG_ARCH_C29X)
433 #define CONFIG_FSL_SDHC_V2_3
434 #define CONFIG_TSECV2_1
435 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
436 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
437 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
441 #if !defined(CONFIG_ARCH_C29X)
442 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
445 #endif /* _ASM_MPC85xx_CONFIG_H_ */