2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
13 * This macro should be removed when we no longer care about backwards
14 * compatibility with older operating systems.
16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
18 #include <fsl_ddrc_version.h>
19 #define CONFIG_SYS_FSL_DDR_BE
22 #define CONFIG_SYS_FSL_IFC_BE
23 #define CONFIG_SYS_FSL_SEC_BE
24 #define CONFIG_SYS_FSL_SFP_BE
25 #define CONFIG_SYS_FSL_SEC_MON_BE
27 #if defined(CONFIG_ARCH_MPC8536)
28 #define CONFIG_SYS_FSL_SEC_COMPAT 2
29 #define CONFIG_SYS_FSL_ERRATUM_A004508
30 #define CONFIG_SYS_FSL_ERRATUM_A005125
32 #elif defined(CONFIG_ARCH_MPC8540)
33 #define CONFIG_SYS_FSL_DDRC_GEN1
35 #elif defined(CONFIG_ARCH_MPC8541)
36 #define CONFIG_SYS_FSL_DDRC_GEN1
37 #define CONFIG_SYS_FSL_SEC_COMPAT 2
39 #elif defined(CONFIG_ARCH_MPC8544)
40 #define CONFIG_SYS_FSL_DDRC_GEN2
41 #define CONFIG_SYS_FSL_SEC_COMPAT 2
42 #define CONFIG_SYS_FSL_ERRATUM_A005125
44 #elif defined(CONFIG_ARCH_MPC8548)
45 #define CONFIG_SYS_FSL_DDRC_GEN2
46 #define CONFIG_SYS_FSL_SEC_COMPAT 2
47 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
48 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
49 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
50 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
51 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
52 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
53 #define CONFIG_SYS_FSL_RMU
54 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
55 #define CONFIG_SYS_FSL_ERRATUM_A005125
56 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
57 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
59 #elif defined(CONFIG_ARCH_MPC8555)
60 #define CONFIG_SYS_FSL_DDRC_GEN1
61 #define CONFIG_SYS_FSL_SEC_COMPAT 2
63 #elif defined(CONFIG_ARCH_MPC8560)
64 #define CONFIG_SYS_FSL_DDRC_GEN1
66 #elif defined(CONFIG_ARCH_MPC8568)
67 #define CONFIG_SYS_FSL_DDRC_GEN2
68 #define CONFIG_SYS_FSL_SEC_COMPAT 2
69 #define QE_MURAM_SIZE 0x10000UL
71 #define QE_NUM_OF_SNUM 28
72 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
73 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
74 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
75 #define CONFIG_SYS_FSL_RMU
76 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
78 #elif defined(CONFIG_ARCH_MPC8569)
79 #define CONFIG_SYS_FSL_SEC_COMPAT 2
80 #define QE_MURAM_SIZE 0x20000UL
82 #define QE_NUM_OF_SNUM 46
83 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
84 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
85 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
86 #define CONFIG_SYS_FSL_RMU
87 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
88 #define CONFIG_SYS_FSL_ERRATUM_A004508
89 #define CONFIG_SYS_FSL_ERRATUM_A005125
91 #elif defined(CONFIG_ARCH_MPC8572)
92 #define CONFIG_SYS_FSL_SEC_COMPAT 2
93 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
94 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
95 #define CONFIG_SYS_FSL_ERRATUM_A004508
96 #define CONFIG_SYS_FSL_ERRATUM_A005125
98 #elif defined(CONFIG_ARCH_P1010)
99 #define CONFIG_FSL_SDHC_V2_3
100 #define CONFIG_TSECV2
101 #define CONFIG_SYS_FSL_SEC_COMPAT 4
102 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
103 #define CONFIG_NUM_DDR_CONTROLLERS 1
104 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
105 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
106 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
107 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
108 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
109 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
110 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
111 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
112 #define CONFIG_SYS_FSL_ERRATUM_A005125
113 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
114 #define CONFIG_SYS_FSL_ERRATUM_A004508
115 #define CONFIG_SYS_FSL_ERRATUM_A007075
116 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
117 #define CONFIG_SYS_FSL_ERRATUM_A006261
118 #define CONFIG_SYS_FSL_ERRATUM_A004477
119 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
120 #define CONFIG_ESDHC_HC_BLK_ADDR
122 /* P1011 is single core version of P1020 */
123 #elif defined(CONFIG_ARCH_P1011)
124 #define CONFIG_TSECV2
125 #define CONFIG_FSL_PCIE_DISABLE_ASPM
126 #define CONFIG_SYS_FSL_SEC_COMPAT 2
127 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
128 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
129 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
130 #define CONFIG_SYS_FSL_ERRATUM_A004508
131 #define CONFIG_SYS_FSL_ERRATUM_A005125
133 #elif defined(CONFIG_ARCH_P1020)
134 #define CONFIG_TSECV2
135 #define CONFIG_FSL_PCIE_DISABLE_ASPM
136 #define CONFIG_SYS_FSL_SEC_COMPAT 2
137 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
138 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
139 #define CONFIG_SYS_FSL_ERRATUM_A004508
140 #define CONFIG_SYS_FSL_ERRATUM_A005125
141 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
142 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
145 #elif defined(CONFIG_ARCH_P1021)
146 #define CONFIG_TSECV2
147 #define CONFIG_FSL_PCIE_DISABLE_ASPM
148 #define CONFIG_SYS_FSL_SEC_COMPAT 2
149 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
151 #define QE_MURAM_SIZE 0x6000UL
152 #define MAX_QE_RISC 1
153 #define QE_NUM_OF_SNUM 28
154 #define CONFIG_SYS_FSL_ERRATUM_A004508
155 #define CONFIG_SYS_FSL_ERRATUM_A005125
156 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
158 #elif defined(CONFIG_ARCH_P1022)
159 #define CONFIG_TSECV2
160 #define CONFIG_SYS_FSL_SEC_COMPAT 2
161 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
162 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
163 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
164 #define CONFIG_FSL_SATA_ERRATUM_A001
165 #define CONFIG_SYS_FSL_ERRATUM_A004508
166 #define CONFIG_SYS_FSL_ERRATUM_A005125
167 #define CONFIG_SYS_FSL_ERRATUM_A004477
169 #elif defined(CONFIG_ARCH_P1023)
170 #define CONFIG_SYS_FSL_SEC_COMPAT 4
171 #define CONFIG_SYS_NUM_FMAN 1
172 #define CONFIG_SYS_NUM_FM1_DTSEC 2
173 #define CONFIG_NUM_DDR_CONTROLLERS 1
174 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
175 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
176 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
177 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
178 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
179 #define CONFIG_SYS_FSL_ERRATUM_A004508
180 #define CONFIG_SYS_FSL_ERRATUM_A005125
181 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
182 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
184 /* P1024 is lower end variant of P1020 */
185 #elif defined(CONFIG_ARCH_P1024)
186 #define CONFIG_TSECV2
187 #define CONFIG_FSL_PCIE_DISABLE_ASPM
188 #define CONFIG_SYS_FSL_SEC_COMPAT 2
189 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
190 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
191 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
192 #define CONFIG_SYS_FSL_ERRATUM_A004508
193 #define CONFIG_SYS_FSL_ERRATUM_A005125
195 /* P1025 is lower end variant of P1021 */
196 #elif defined(CONFIG_ARCH_P1025)
197 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
198 #define CONFIG_TSECV2
199 #define CONFIG_FSL_PCIE_DISABLE_ASPM
200 #define CONFIG_SYS_FSL_SEC_COMPAT 2
201 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
202 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
203 #define QE_MURAM_SIZE 0x6000UL
204 #define MAX_QE_RISC 1
205 #define QE_NUM_OF_SNUM 28
206 #define CONFIG_SYS_FSL_ERRATUM_A004508
207 #define CONFIG_SYS_FSL_ERRATUM_A005125
209 #elif defined(CONFIG_ARCH_P2020)
210 #define CONFIG_SYS_FSL_SEC_COMPAT 2
211 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
212 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
213 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
214 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
215 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
216 #define CONFIG_SYS_FSL_RMU
217 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
218 #define CONFIG_SYS_FSL_ERRATUM_A004508
219 #define CONFIG_SYS_FSL_ERRATUM_A005125
220 #define CONFIG_SYS_FSL_ERRATUM_A004477
221 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
223 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
224 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
225 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
226 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
227 #define CONFIG_SYS_FSL_SEC_COMPAT 4
228 #define CONFIG_SYS_NUM_FMAN 1
229 #define CONFIG_SYS_NUM_FM1_DTSEC 5
230 #define CONFIG_SYS_NUM_FM1_10GEC 1
231 #define CONFIG_NUM_DDR_CONTROLLERS 1
232 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
233 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
234 #define CONFIG_SYS_FSL_TBCLK_DIV 32
235 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
236 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
237 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
238 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
239 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
240 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
241 #define CONFIG_SYS_FSL_ERRATUM_USB14
242 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
243 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
244 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
245 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
246 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
247 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
248 #define CONFIG_SYS_FSL_ERRATUM_A004510
249 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
250 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
251 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
252 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
253 #define CONFIG_SYS_FSL_ERRATUM_A004849
254 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
255 #define CONFIG_SYS_FSL_ERRATUM_A006261
256 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
258 #elif defined(CONFIG_ARCH_P3041)
259 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
260 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
261 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
262 #define CONFIG_SYS_FSL_SEC_COMPAT 4
263 #define CONFIG_SYS_NUM_FMAN 1
264 #define CONFIG_SYS_NUM_FM1_DTSEC 5
265 #define CONFIG_SYS_NUM_FM1_10GEC 1
266 #define CONFIG_NUM_DDR_CONTROLLERS 1
267 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
268 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
269 #define CONFIG_SYS_FSL_TBCLK_DIV 32
270 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
271 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
272 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
273 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
274 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
275 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
276 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
277 #define CONFIG_SYS_FSL_ERRATUM_USB14
278 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
279 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
280 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
281 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
282 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
283 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
284 #define CONFIG_SYS_FSL_ERRATUM_A004510
285 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
286 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
287 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
288 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
289 #define CONFIG_SYS_FSL_ERRATUM_A004849
290 #define CONFIG_SYS_FSL_ERRATUM_A005812
291 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
292 #define CONFIG_SYS_FSL_ERRATUM_A006261
293 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
295 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
296 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
297 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
298 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
299 #define CONFIG_SYS_FSL_SEC_COMPAT 4
300 #define CONFIG_SYS_NUM_FMAN 2
301 #define CONFIG_SYS_NUM_FM1_DTSEC 4
302 #define CONFIG_SYS_NUM_FM2_DTSEC 4
303 #define CONFIG_SYS_NUM_FM1_10GEC 1
304 #define CONFIG_SYS_NUM_FM2_10GEC 1
305 #define CONFIG_NUM_DDR_CONTROLLERS 2
306 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
307 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
308 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
309 #define CONFIG_SYS_FSL_TBCLK_DIV 16
310 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
311 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
312 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
313 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
314 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
315 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
316 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
317 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
318 #define CONFIG_SYS_P4080_ERRATUM_CPU22
319 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
320 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
321 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
322 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
323 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
324 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
325 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
326 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
327 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
328 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
329 #define CONFIG_SYS_FSL_RMU
330 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
331 #define CONFIG_SYS_FSL_ERRATUM_A004510
332 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
333 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
334 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
335 #define CONFIG_SYS_FSL_ERRATUM_A004849
336 #define CONFIG_SYS_FSL_ERRATUM_A004580
337 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
338 #define CONFIG_SYS_FSL_ERRATUM_A005812
339 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
340 #define CONFIG_SYS_FSL_ERRATUM_A007075
341 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
343 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
344 #define CONFIG_SYS_PPC64 /* 64-bit core */
345 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
346 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
347 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
348 #define CONFIG_SYS_FSL_SEC_COMPAT 4
349 #define CONFIG_SYS_NUM_FMAN 1
350 #define CONFIG_SYS_NUM_FM1_DTSEC 5
351 #define CONFIG_SYS_NUM_FM1_10GEC 1
352 #define CONFIG_NUM_DDR_CONTROLLERS 2
353 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
354 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
355 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
356 #define CONFIG_SYS_FSL_TBCLK_DIV 32
357 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
358 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
359 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
360 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
361 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
362 #define CONFIG_SYS_FSL_ERRATUM_USB14
363 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
364 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
365 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
366 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
367 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
368 #define CONFIG_SYS_FSL_ERRATUM_A004510
369 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
370 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
371 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
372 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
373 #define CONFIG_SYS_FSL_ERRATUM_A006261
374 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
376 #elif defined(CONFIG_ARCH_P5040)
377 #define CONFIG_SYS_PPC64
378 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
379 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
380 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
381 #define CONFIG_SYS_FSL_SEC_COMPAT 4
382 #define CONFIG_SYS_NUM_FMAN 2
383 #define CONFIG_SYS_NUM_FM1_DTSEC 5
384 #define CONFIG_SYS_NUM_FM1_10GEC 1
385 #define CONFIG_SYS_NUM_FM2_DTSEC 5
386 #define CONFIG_SYS_NUM_FM2_10GEC 1
387 #define CONFIG_NUM_DDR_CONTROLLERS 2
388 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
389 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
390 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
391 #define CONFIG_SYS_FSL_TBCLK_DIV 16
392 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
393 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
394 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
395 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
396 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
397 #define CONFIG_SYS_FSL_ERRATUM_USB14
398 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
399 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
400 #define CONFIG_SYS_FSL_ERRATUM_A004699
401 #define CONFIG_SYS_FSL_ERRATUM_A004510
402 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
403 #define CONFIG_SYS_FSL_ERRATUM_A006261
404 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
405 #define CONFIG_SYS_FSL_ERRATUM_A005812
407 #elif defined(CONFIG_ARCH_BSC9131)
408 #define CONFIG_FSL_SDHC_V2_3
409 #define CONFIG_TSECV2
410 #define CONFIG_SYS_FSL_SEC_COMPAT 4
411 #define CONFIG_NUM_DDR_CONTROLLERS 1
412 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
413 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
414 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
415 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
416 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
417 #define CONFIG_NAND_FSL_IFC
418 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
419 #define CONFIG_SYS_FSL_ERRATUM_A005125
420 #define CONFIG_SYS_FSL_ERRATUM_A004477
421 #define CONFIG_ESDHC_HC_BLK_ADDR
423 #elif defined(CONFIG_ARCH_BSC9132)
424 #define CONFIG_FSL_SDHC_V2_3
425 #define CONFIG_TSECV2
426 #define CONFIG_SYS_FSL_SEC_COMPAT 4
427 #define CONFIG_NUM_DDR_CONTROLLERS 2
428 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
429 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
430 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
431 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
432 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
433 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
434 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
435 #define CONFIG_NAND_FSL_IFC
436 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
437 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
438 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
439 #define CONFIG_SYS_FSL_ERRATUM_A005125
440 #define CONFIG_SYS_FSL_ERRATUM_A005434
441 #define CONFIG_SYS_FSL_ERRATUM_A004477
442 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
443 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
444 #define CONFIG_ESDHC_HC_BLK_ADDR
446 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
448 #define CONFIG_SYS_PPC64 /* 64-bit core */
449 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
450 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
451 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
452 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
453 #ifdef CONFIG_ARCH_T4240
454 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
455 #define CONFIG_SYS_NUM_FM1_DTSEC 8
456 #define CONFIG_SYS_NUM_FM1_10GEC 2
457 #define CONFIG_SYS_NUM_FM2_DTSEC 8
458 #define CONFIG_SYS_NUM_FM2_10GEC 2
459 #define CONFIG_NUM_DDR_CONTROLLERS 3
460 #define CONFIG_SYS_FSL_ERRATUM_A006261
462 #define CONFIG_SYS_NUM_FM1_DTSEC 6
463 #define CONFIG_SYS_NUM_FM1_10GEC 1
464 #define CONFIG_SYS_NUM_FM2_DTSEC 8
465 #define CONFIG_SYS_NUM_FM2_10GEC 1
466 #define CONFIG_NUM_DDR_CONTROLLERS 2
467 #if defined(CONFIG_ARCH_T4160)
468 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
471 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
472 #define CONFIG_SYS_FSL_SRDS_1
473 #define CONFIG_SYS_FSL_SRDS_2
474 #define CONFIG_SYS_FSL_SRDS_3
475 #define CONFIG_SYS_FSL_SRDS_4
476 #define CONFIG_SYS_FSL_SEC_COMPAT 4
477 #define CONFIG_SYS_NUM_FMAN 2
478 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
479 #define CONFIG_SYS_PME_CLK 0
480 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
481 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
482 #define CONFIG_SYS_FMAN_V3
483 #define CONFIG_SYS_FM1_CLK 3
484 #define CONFIG_SYS_FM2_CLK 3
485 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
486 #define CONFIG_SYS_FSL_TBCLK_DIV 16
487 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
488 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
489 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
490 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
491 #define CONFIG_SYS_FSL_SRIO_LIODN
492 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
493 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
494 #define CONFIG_SYS_FSL_ERRATUM_A004468
495 #define CONFIG_SYS_FSL_ERRATUM_A005871
496 #define CONFIG_SYS_FSL_ERRATUM_A006379
497 #define CONFIG_SYS_FSL_ERRATUM_A007186
498 #define CONFIG_SYS_FSL_ERRATUM_A006593
499 #define CONFIG_SYS_FSL_ERRATUM_A007798
500 #define CONFIG_SYS_FSL_ERRATUM_A009942
501 #define CONFIG_SYS_FSL_SFP_VER_3_0
502 #define CONFIG_SYS_FSL_PCI_VER_3_X
504 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
506 #define CONFIG_SYS_PPC64 /* 64-bit core */
507 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
508 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
509 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
510 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
511 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
512 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
513 #define CONFIG_SYS_FSL_SRDS_1
514 #define CONFIG_SYS_FSL_SRDS_2
515 #define CONFIG_SYS_MAPLE
516 #define CONFIG_SYS_CPRI
517 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
518 #define CONFIG_SYS_FSL_SEC_COMPAT 4
519 #define CONFIG_SYS_NUM_FMAN 1
520 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
521 #define CONFIG_SYS_FM1_CLK 0
522 #define CONFIG_SYS_CPRI_CLK 3
523 #define CONFIG_SYS_ULB_CLK 4
524 #define CONFIG_SYS_ETVPE_CLK 1
525 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
526 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
527 #define CONFIG_SYS_FMAN_V3
528 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
529 #define CONFIG_SYS_FSL_TBCLK_DIV 16
530 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
531 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
532 #define CONFIG_SYS_FSL_ERRATUM_A005871
533 #define CONFIG_SYS_FSL_ERRATUM_A006379
534 #define CONFIG_SYS_FSL_ERRATUM_A007186
535 #define CONFIG_SYS_FSL_ERRATUM_A006593
536 #define CONFIG_SYS_FSL_ERRATUM_A007075
537 #define CONFIG_SYS_FSL_ERRATUM_A006475
538 #define CONFIG_SYS_FSL_ERRATUM_A006384
539 #define CONFIG_SYS_FSL_ERRATUM_A007212
540 #define CONFIG_SYS_FSL_ERRATUM_A004477
541 #define CONFIG_SYS_FSL_ERRATUM_A009942
542 #define CONFIG_SYS_FSL_SFP_VER_3_0
544 #ifdef CONFIG_ARCH_B4860
545 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
546 #define CONFIG_MAX_DSP_CPUS 12
547 #define CONFIG_NUM_DSP_CPUS 6
548 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
549 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
550 #define CONFIG_SYS_NUM_FM1_DTSEC 6
551 #define CONFIG_SYS_NUM_FM1_10GEC 2
552 #define CONFIG_NUM_DDR_CONTROLLERS 2
553 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
554 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
555 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
556 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
557 #define CONFIG_SYS_FSL_SRIO_LIODN
559 #define CONFIG_MAX_DSP_CPUS 2
560 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
561 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
562 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
563 #define CONFIG_SYS_NUM_FM1_DTSEC 4
564 #define CONFIG_SYS_NUM_FM1_10GEC 0
565 #define CONFIG_NUM_DDR_CONTROLLERS 1
568 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
569 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
571 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
572 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
573 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
574 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
575 #ifdef CONFIG_SYS_FSL_DDR4
576 #define CONFIG_SYS_FSL_DDRC_GEN4
578 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
579 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
580 #define CONFIG_SYS_FSL_SRDS_1
581 #define CONFIG_SYS_FSL_SEC_COMPAT 5
582 #define CONFIG_SYS_NUM_FMAN 1
583 #define CONFIG_SYS_NUM_FM1_DTSEC 5
584 #define CONFIG_NUM_DDR_CONTROLLERS 1
585 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
586 #define CONFIG_PME_PLAT_CLK_DIV 2
587 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
588 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
589 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
590 #define CONFIG_SYS_FSL_ERRATUM_A008044
591 #define CONFIG_SYS_FMAN_V3
592 #define CONFIG_FM_PLAT_CLK_DIV 1
593 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
594 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
595 per rcw field value */
596 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
597 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
598 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
599 #define CONFIG_SYS_FSL_TBCLK_DIV 16
600 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
601 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
602 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
603 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
604 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
605 #define QE_MURAM_SIZE 0x6000UL
606 #define MAX_QE_RISC 1
607 #define QE_NUM_OF_SNUM 28
608 #define CONFIG_SYS_FSL_SFP_VER_3_0
609 #define CONFIG_SYS_FSL_ERRATUM_A008378
610 #define CONFIG_SYS_FSL_ERRATUM_A009663
611 #define CONFIG_SYS_FSL_ERRATUM_A009942
613 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
614 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
616 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
617 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
618 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
619 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
620 #define CONFIG_SYS_FMAN_V3
621 #ifdef CONFIG_SYS_FSL_DDR4
622 #define CONFIG_SYS_FSL_DDRC_GEN4
624 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
625 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
626 #define CONFIG_SYS_FSL_SRDS_1
627 #define CONFIG_SYS_FSL_SEC_COMPAT 5
628 #define CONFIG_SYS_NUM_FMAN 1
629 #define CONFIG_SYS_NUM_FM1_DTSEC 4
630 #define CONFIG_SYS_NUM_FM1_10GEC 1
631 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
632 #define CONFIG_NUM_DDR_CONTROLLERS 1
633 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
634 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
635 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
636 #define CONFIG_SYS_FM1_CLK 0
637 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
638 per rcw field value */
639 #define CONFIG_QBMAN_CLK_DIV 1
640 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
641 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
642 #define CONFIG_SYS_FSL_TBCLK_DIV 16
643 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
644 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
645 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
646 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
647 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
648 #define QE_MURAM_SIZE 0x6000UL
649 #define MAX_QE_RISC 1
650 #define QE_NUM_OF_SNUM 28
651 #define CONFIG_SYS_FSL_SFP_VER_3_0
652 #define CONFIG_SYS_FSL_ERRATUM_A008378
653 #define CONFIG_SYS_FSL_ERRATUM_A009663
654 #define CONFIG_SYS_FSL_ERRATUM_A009942
656 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
658 #define CONFIG_SYS_PPC64 /* 64-bit core */
659 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
660 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
661 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
662 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
663 #define CONFIG_SYS_FSL_QMAN_V3
664 #define CONFIG_SYS_FSL_SEC_COMPAT 4
665 #define CONFIG_SYS_NUM_FMAN 1
666 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
667 #define CONFIG_SYS_FSL_SRDS_1
668 #define CONFIG_SYS_FSL_PCI_VER_3_X
669 #if defined(CONFIG_ARCH_T2080)
670 #define CONFIG_SYS_NUM_FM1_DTSEC 8
671 #define CONFIG_SYS_NUM_FM1_10GEC 4
672 #define CONFIG_SYS_FSL_SRDS_2
673 #define CONFIG_SYS_FSL_SRIO_LIODN
674 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
675 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
676 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
677 #elif defined(CONFIG_ARCH_T2081)
678 #define CONFIG_SYS_NUM_FM1_DTSEC 6
679 #define CONFIG_SYS_NUM_FM1_10GEC 2
681 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
682 #define CONFIG_NUM_DDR_CONTROLLERS 1
683 #define CONFIG_PME_PLAT_CLK_DIV 1
684 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
685 #define CONFIG_SYS_FM1_CLK 0
686 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
687 per rcw field value */
688 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
689 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
690 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
691 #define CONFIG_SYS_FMAN_V3
692 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
693 #define CONFIG_SYS_FSL_TBCLK_DIV 16
694 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
695 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
696 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
697 #define CONFIG_SYS_FSL_ERRATUM_A007212
698 #define CONFIG_SYS_FSL_SFP_VER_3_0
699 #define CONFIG_SYS_FSL_ISBC_VER 2
700 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
701 #define CONFIG_SYS_FSL_ERRATUM_A006593
702 #define CONFIG_SYS_FSL_ERRATUM_A007186
703 #define CONFIG_SYS_FSL_ERRATUM_A006379
704 #define CONFIG_SYS_FSL_ERRATUM_A009942
705 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
706 #define CONFIG_SYS_FSL_SFP_VER_3_0
709 #elif defined(CONFIG_ARCH_C29X)
710 #define CONFIG_FSL_SDHC_V2_3
711 #define CONFIG_TSECV2_1
712 #define CONFIG_SYS_FSL_SEC_COMPAT 6
713 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
714 #define CONFIG_NUM_DDR_CONTROLLERS 1
715 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
716 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
717 #define CONFIG_SYS_FSL_ERRATUM_A005125
718 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
719 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
721 #elif defined(CONFIG_ARCH_QEMU_E500)
724 #error Processor type not defined for this platform
728 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
730 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
733 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
734 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
735 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
736 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
737 #define CONFIG_SYS_FSL_DDRC_GEN3
740 #if !defined(CONFIG_ARCH_C29X)
741 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
744 #endif /* _ASM_MPC85xx_CONFIG_H_ */