2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _ASM_MPC85xx_CONFIG_H_
22 #define _ASM_MPC85xx_CONFIG_H_
24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
30 /* Number of TLB CAM entries we have on FSL Book-E chips */
31 #if defined(CONFIG_E500MC)
32 #define CONFIG_SYS_NUM_TLBCAMS 64
33 #elif defined(CONFIG_E500)
34 #define CONFIG_SYS_NUM_TLBCAMS 16
37 #if defined(CONFIG_MPC8536)
38 #define CONFIG_MAX_CPUS 1
39 #define CONFIG_SYS_FSL_NUM_LAWS 12
40 #define CONFIG_SYS_FSL_SEC_COMPAT 2
41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
43 #elif defined(CONFIG_MPC8540)
44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
48 #elif defined(CONFIG_MPC8541)
49 #define CONFIG_MAX_CPUS 1
50 #define CONFIG_SYS_FSL_NUM_LAWS 8
51 #define CONFIG_SYS_FSL_SEC_COMPAT 2
52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
54 #elif defined(CONFIG_MPC8544)
55 #define CONFIG_MAX_CPUS 1
56 #define CONFIG_SYS_FSL_NUM_LAWS 10
57 #define CONFIG_SYS_FSL_SEC_COMPAT 2
58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
60 #elif defined(CONFIG_MPC8548)
61 #define CONFIG_MAX_CPUS 1
62 #define CONFIG_SYS_FSL_NUM_LAWS 10
63 #define CONFIG_SYS_FSL_SEC_COMPAT 2
64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
67 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
68 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
69 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
70 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
71 #define CONFIG_SYS_FSL_RMU
72 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
74 #elif defined(CONFIG_MPC8555)
75 #define CONFIG_MAX_CPUS 1
76 #define CONFIG_SYS_FSL_NUM_LAWS 8
77 #define CONFIG_SYS_FSL_SEC_COMPAT 2
78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
80 #elif defined(CONFIG_MPC8560)
81 #define CONFIG_MAX_CPUS 1
82 #define CONFIG_SYS_FSL_NUM_LAWS 8
83 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
85 #elif defined(CONFIG_MPC8568)
86 #define CONFIG_MAX_CPUS 1
87 #define CONFIG_SYS_FSL_NUM_LAWS 10
88 #define CONFIG_SYS_FSL_SEC_COMPAT 2
89 #define QE_MURAM_SIZE 0x10000UL
91 #define QE_NUM_OF_SNUM 28
92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
93 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
94 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
95 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
96 #define CONFIG_SYS_FSL_RMU
97 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
99 #elif defined(CONFIG_MPC8569)
100 #define CONFIG_MAX_CPUS 1
101 #define CONFIG_SYS_FSL_NUM_LAWS 10
102 #define CONFIG_SYS_FSL_SEC_COMPAT 2
103 #define QE_MURAM_SIZE 0x20000UL
104 #define MAX_QE_RISC 4
105 #define QE_NUM_OF_SNUM 46
106 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
107 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
108 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
109 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
110 #define CONFIG_SYS_FSL_RMU
111 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
113 #elif defined(CONFIG_MPC8572)
114 #define CONFIG_MAX_CPUS 2
115 #define CONFIG_SYS_FSL_NUM_LAWS 12
116 #define CONFIG_SYS_FSL_SEC_COMPAT 2
117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
118 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
119 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
121 #elif defined(CONFIG_P1010)
122 #define CONFIG_MAX_CPUS 1
123 #define CONFIG_FSL_SDHC_V2_3
124 #define CONFIG_SYS_FSL_NUM_LAWS 12
125 #define CONFIG_TSECV2
126 #define CONFIG_SYS_FSL_SEC_COMPAT 4
127 #define CONFIG_FSL_SATA_V2
128 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
129 #define CONFIG_NUM_DDR_CONTROLLERS 1
130 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
131 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
132 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
133 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
134 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
135 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
137 /* P1011 is single core version of P1020 */
138 #elif defined(CONFIG_P1011)
139 #define CONFIG_MAX_CPUS 1
140 #define CONFIG_SYS_FSL_NUM_LAWS 12
141 #define CONFIG_TSECV2
142 #define CONFIG_FSL_PCIE_DISABLE_ASPM
143 #define CONFIG_SYS_FSL_SEC_COMPAT 2
144 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
145 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
146 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
148 /* P1012 is single core version of P1021 */
149 #elif defined(CONFIG_P1012)
150 #define CONFIG_MAX_CPUS 1
151 #define CONFIG_SYS_FSL_NUM_LAWS 12
152 #define CONFIG_TSECV2
153 #define CONFIG_FSL_PCIE_DISABLE_ASPM
154 #define CONFIG_SYS_FSL_SEC_COMPAT 2
155 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
156 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
157 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
158 #define QE_MURAM_SIZE 0x6000UL
159 #define MAX_QE_RISC 1
160 #define QE_NUM_OF_SNUM 28
162 /* P1013 is single core version of P1022 */
163 #elif defined(CONFIG_P1013)
164 #define CONFIG_MAX_CPUS 1
165 #define CONFIG_SYS_FSL_NUM_LAWS 12
166 #define CONFIG_TSECV2
167 #define CONFIG_SYS_FSL_SEC_COMPAT 2
168 #define CONFIG_FSL_SATA_V2
169 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
170 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
171 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
172 #define CONFIG_FSL_SATA_ERRATUM_A001
174 #elif defined(CONFIG_P1014)
175 #define CONFIG_MAX_CPUS 1
176 #define CONFIG_FSL_SDHC_V2_3
177 #define CONFIG_SYS_FSL_NUM_LAWS 12
178 #define CONFIG_TSECV2
179 #define CONFIG_SYS_FSL_SEC_COMPAT 4
180 #define CONFIG_FSL_SATA_V2
181 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
182 #define CONFIG_NUM_DDR_CONTROLLERS 1
183 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
184 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
185 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
186 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
187 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
189 /* P1015 is single core version of P1024 */
190 #elif defined(CONFIG_P1015)
191 #define CONFIG_MAX_CPUS 1
192 #define CONFIG_SYS_FSL_NUM_LAWS 12
193 #define CONFIG_TSECV2
194 #define CONFIG_FSL_PCIE_DISABLE_ASPM
195 #define CONFIG_SYS_FSL_SEC_COMPAT 2
196 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
197 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
198 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
200 /* P1016 is single core version of P1025 */
201 #elif defined(CONFIG_P1016)
202 #define CONFIG_MAX_CPUS 1
203 #define CONFIG_SYS_FSL_NUM_LAWS 12
204 #define CONFIG_TSECV2
205 #define CONFIG_FSL_PCIE_DISABLE_ASPM
206 #define CONFIG_SYS_FSL_SEC_COMPAT 2
207 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
208 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
209 #define QE_MURAM_SIZE 0x6000UL
210 #define MAX_QE_RISC 1
211 #define QE_NUM_OF_SNUM 28
212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
214 /* P1017 is single core version of P1023 */
215 #elif defined(CONFIG_P1017)
216 #define CONFIG_MAX_CPUS 1
217 #define CONFIG_SYS_FSL_NUM_LAWS 12
218 #define CONFIG_SYS_FSL_SEC_COMPAT 4
219 #define CONFIG_SYS_NUM_FMAN 1
220 #define CONFIG_SYS_NUM_FM1_DTSEC 2
221 #define CONFIG_NUM_DDR_CONTROLLERS 1
222 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
223 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
224 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
225 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
228 #elif defined(CONFIG_P1020)
229 #define CONFIG_MAX_CPUS 2
230 #define CONFIG_SYS_FSL_NUM_LAWS 12
231 #define CONFIG_TSECV2
232 #define CONFIG_FSL_PCIE_DISABLE_ASPM
233 #define CONFIG_SYS_FSL_SEC_COMPAT 2
234 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
235 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
236 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
238 #elif defined(CONFIG_P1021)
239 #define CONFIG_MAX_CPUS 2
240 #define CONFIG_SYS_FSL_NUM_LAWS 12
241 #define CONFIG_TSECV2
242 #define CONFIG_FSL_PCIE_DISABLE_ASPM
243 #define CONFIG_SYS_FSL_SEC_COMPAT 2
244 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
245 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
246 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
247 #define QE_MURAM_SIZE 0x6000UL
248 #define MAX_QE_RISC 1
249 #define QE_NUM_OF_SNUM 28
251 #elif defined(CONFIG_P1022)
252 #define CONFIG_MAX_CPUS 2
253 #define CONFIG_SYS_FSL_NUM_LAWS 12
254 #define CONFIG_TSECV2
255 #define CONFIG_SYS_FSL_SEC_COMPAT 2
256 #define CONFIG_FSL_SATA_V2
257 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
258 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
259 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
260 #define CONFIG_FSL_SATA_ERRATUM_A001
262 #elif defined(CONFIG_P1023)
263 #define CONFIG_MAX_CPUS 2
264 #define CONFIG_SYS_FSL_NUM_LAWS 12
265 #define CONFIG_SYS_FSL_SEC_COMPAT 4
266 #define CONFIG_SYS_NUM_FMAN 1
267 #define CONFIG_SYS_NUM_FM1_DTSEC 2
268 #define CONFIG_NUM_DDR_CONTROLLERS 1
269 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
270 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
271 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
272 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
273 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
275 /* P1024 is lower end variant of P1020 */
276 #elif defined(CONFIG_P1024)
277 #define CONFIG_MAX_CPUS 2
278 #define CONFIG_SYS_FSL_NUM_LAWS 12
279 #define CONFIG_TSECV2
280 #define CONFIG_FSL_PCIE_DISABLE_ASPM
281 #define CONFIG_SYS_FSL_SEC_COMPAT 2
282 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
283 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
284 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
286 /* P1025 is lower end variant of P1021 */
287 #elif defined(CONFIG_P1025)
288 #define CONFIG_MAX_CPUS 2
289 #define CONFIG_SYS_FSL_NUM_LAWS 12
290 #define CONFIG_TSECV2
291 #define CONFIG_FSL_PCIE_DISABLE_ASPM
292 #define CONFIG_SYS_FSL_SEC_COMPAT 2
293 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
294 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
296 #define QE_MURAM_SIZE 0x6000UL
297 #define MAX_QE_RISC 1
298 #define QE_NUM_OF_SNUM 28
300 /* P2010 is single core version of P2020 */
301 #elif defined(CONFIG_P2010)
302 #define CONFIG_MAX_CPUS 1
303 #define CONFIG_SYS_FSL_NUM_LAWS 12
304 #define CONFIG_SYS_FSL_SEC_COMPAT 2
305 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
306 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
307 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
309 #elif defined(CONFIG_P2020)
310 #define CONFIG_MAX_CPUS 2
311 #define CONFIG_SYS_FSL_NUM_LAWS 12
312 #define CONFIG_SYS_FSL_SEC_COMPAT 2
313 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
314 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
315 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
316 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
317 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
318 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
319 #define CONFIG_SYS_FSL_RMU
320 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
322 #elif defined(CONFIG_PPC_P2040)
323 #define CONFIG_MAX_CPUS 4
324 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
325 #define CONFIG_SYS_FSL_NUM_LAWS 32
326 #define CONFIG_SYS_FSL_SEC_COMPAT 4
327 #define CONFIG_SYS_NUM_FMAN 1
328 #define CONFIG_SYS_NUM_FM1_DTSEC 5
329 #define CONFIG_NUM_DDR_CONTROLLERS 1
330 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
331 #define CONFIG_SYS_FSL_TBCLK_DIV 32
332 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
333 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
334 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
335 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
336 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
337 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
338 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
339 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
340 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
341 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
342 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
344 #elif defined(CONFIG_PPC_P2041)
345 #define CONFIG_MAX_CPUS 4
346 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
347 #define CONFIG_SYS_FSL_NUM_LAWS 32
348 #define CONFIG_SYS_FSL_SEC_COMPAT 4
349 #define CONFIG_FSL_SATA_V2
350 #define CONFIG_SYS_NUM_FMAN 1
351 #define CONFIG_SYS_NUM_FM1_DTSEC 5
352 #define CONFIG_SYS_NUM_FM1_10GEC 1
353 #define CONFIG_NUM_DDR_CONTROLLERS 1
354 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
355 #define CONFIG_SYS_FSL_TBCLK_DIV 32
356 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
357 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
358 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
359 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
360 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
361 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
362 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
363 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
364 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
365 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
366 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
368 #elif defined(CONFIG_PPC_P3041)
369 #define CONFIG_MAX_CPUS 4
370 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
371 #define CONFIG_SYS_FSL_NUM_LAWS 32
372 #define CONFIG_SYS_FSL_SEC_COMPAT 4
373 #define CONFIG_FSL_SATA_V2
374 #define CONFIG_SYS_NUM_FMAN 1
375 #define CONFIG_SYS_NUM_FM1_DTSEC 5
376 #define CONFIG_SYS_NUM_FM1_10GEC 1
377 #define CONFIG_NUM_DDR_CONTROLLERS 1
378 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
379 #define CONFIG_SYS_FSL_TBCLK_DIV 32
380 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
381 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
382 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
383 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
384 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
385 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
386 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
387 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
388 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
389 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
390 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
392 #elif defined(CONFIG_PPC_P3060)
393 #define CONFIG_MAX_CPUS 8
394 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
395 #define CONFIG_SYS_FSL_NUM_LAWS 32
396 #define CONFIG_SYS_FSL_SEC_COMPAT 4
397 #define CONFIG_SYS_NUM_FMAN 2
398 #define CONFIG_SYS_NUM_FM1_DTSEC 4
399 #define CONFIG_SYS_NUM_FM2_DTSEC 4
400 #define CONFIG_NUM_DDR_CONTROLLERS 1
401 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
402 #define CONFIG_SYS_FSL_TBCLK_DIV 16
403 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
404 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
405 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
406 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
407 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
408 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
409 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
411 #elif defined(CONFIG_PPC_P4040)
412 #define CONFIG_MAX_CPUS 4
413 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
414 #define CONFIG_SYS_FSL_NUM_LAWS 32
415 #define CONFIG_SYS_FSL_SEC_COMPAT 4
416 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
417 #define CONFIG_SYS_FSL_TBCLK_DIV 16
418 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
419 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
420 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
421 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
422 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
423 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
424 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
426 #elif defined(CONFIG_PPC_P4080)
427 #define CONFIG_MAX_CPUS 8
428 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
429 #define CONFIG_SYS_FSL_NUM_LAWS 32
430 #define CONFIG_SYS_FSL_SEC_COMPAT 4
431 #define CONFIG_SYS_NUM_FMAN 2
432 #define CONFIG_SYS_NUM_FM1_DTSEC 4
433 #define CONFIG_SYS_NUM_FM2_DTSEC 4
434 #define CONFIG_SYS_NUM_FM1_10GEC 1
435 #define CONFIG_SYS_NUM_FM2_10GEC 1
436 #define CONFIG_NUM_DDR_CONTROLLERS 2
437 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
438 #define CONFIG_SYS_FSL_TBCLK_DIV 16
439 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
440 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
441 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
442 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
443 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
444 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
445 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
446 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
447 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
448 #define CONFIG_SYS_P4080_ERRATUM_CPU22
449 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
450 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
451 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
452 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
453 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
454 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
455 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
456 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
457 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
458 #define CONFIG_SYS_FSL_RMU
459 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
461 /* P5010 is single core version of P5020 */
462 #elif defined(CONFIG_PPC_P5010)
463 #define CONFIG_MAX_CPUS 1
464 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
465 #define CONFIG_SYS_FSL_NUM_LAWS 32
466 #define CONFIG_SYS_FSL_SEC_COMPAT 4
467 #define CONFIG_FSL_SATA_V2
468 #define CONFIG_SYS_NUM_FMAN 1
469 #define CONFIG_SYS_NUM_FM1_DTSEC 5
470 #define CONFIG_SYS_NUM_FM1_10GEC 1
471 #define CONFIG_NUM_DDR_CONTROLLERS 1
472 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
473 #define CONFIG_SYS_FSL_TBCLK_DIV 32
474 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
475 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
476 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
477 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
478 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
479 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
480 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
481 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
482 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
483 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
485 #elif defined(CONFIG_PPC_P5020)
486 #define CONFIG_MAX_CPUS 2
487 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
488 #define CONFIG_SYS_FSL_NUM_LAWS 32
489 #define CONFIG_SYS_FSL_SEC_COMPAT 4
490 #define CONFIG_FSL_SATA_V2
491 #define CONFIG_SYS_NUM_FMAN 1
492 #define CONFIG_SYS_NUM_FM1_DTSEC 5
493 #define CONFIG_SYS_NUM_FM1_10GEC 1
494 #define CONFIG_NUM_DDR_CONTROLLERS 2
495 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
496 #define CONFIG_SYS_FSL_TBCLK_DIV 32
497 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
498 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
499 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
500 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
501 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
502 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
503 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
504 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
505 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
506 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
509 #error Processor type not defined for this platform
512 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
513 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
516 #endif /* _ASM_MPC85xx_CONFIG_H_ */