1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 #include <asm/config_mpc85xx.h>
14 #include <asm/config_mpc86xx.h>
20 #ifndef HWCONFIG_BUFFER_SIZE
21 #define HWCONFIG_BUFFER_SIZE 256
24 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
25 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
26 # ifndef CONFIG_HARD_SPI
27 # define CONFIG_HARD_SPI
32 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
34 #ifndef CONFIG_MAX_MEM_MAPPED
35 #if defined(CONFIG_E500) || \
36 defined(CONFIG_MPC86xx) || \
38 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
40 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
44 /* Check if boards need to enable FSL DMA engine for SDRAM init */
45 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
46 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
47 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
48 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
49 #define CONFIG_FSL_DMA
54 * Provide a default boot page translation virtual address that lines up with
55 * Freescale's default e500 reset page.
57 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
58 #ifndef CONFIG_BPTR_VIRT_ADDR
59 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000
63 /* Since so many PPC SOCs have a semi-common LBC, define this here */
64 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
65 defined(CONFIG_MPC83xx)
66 #if !defined(CONFIG_FSL_IFC)
67 #define CONFIG_FSL_LBC
71 /* The TSEC driver uses the PHYLIB infrastructure */
72 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
73 #include <config_phylib_all_drivers.h>
74 #endif /* TSEC_ENET */
76 /* The FMAN driver uses the PHYLIB infrastructure */
78 /* All PPC boards must swap IDE bytes */
79 #define CONFIG_IDE_SWAP_IO
81 #if defined(CONFIG_DM_SERIAL)
83 * TODO: Convert this to a clock driver exists that can give us the UART
86 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
89 #endif /* _ASM_CONFIG_H_ */