1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 #include <asm/config_mpc85xx.h>
14 #include <asm/config_mpc86xx.h>
17 #ifndef HWCONFIG_BUFFER_SIZE
18 #define HWCONFIG_BUFFER_SIZE 256
21 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
22 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
23 # ifndef CONFIG_HARD_SPI
24 # define CONFIG_HARD_SPI
29 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
31 #ifndef CONFIG_MAX_MEM_MAPPED
32 #if defined(CONFIG_E500) || \
33 defined(CONFIG_MPC86xx) || \
35 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
37 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
41 /* Check if boards need to enable FSL DMA engine for SDRAM init */
42 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
43 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
44 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
45 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
46 #define CONFIG_FSL_DMA
51 * Provide a default boot page translation virtual address that lines up with
52 * Freescale's default e500 reset page.
54 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
55 #ifndef CONFIG_BPTR_VIRT_ADDR
56 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000
60 /* Since so many PPC SOCs have a semi-common LBC, define this here */
61 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
62 defined(CONFIG_MPC83xx)
63 #if !defined(CONFIG_FSL_IFC)
64 #define CONFIG_FSL_LBC
68 /* The TSEC driver uses the PHYLIB infrastructure */
69 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
70 #include <config_phylib_all_drivers.h>
71 #endif /* TSEC_ENET */
73 /* The FMAN driver uses the PHYLIB infrastructure */
75 /* All PPC boards must swap IDE bytes */
76 #define CONFIG_IDE_SWAP_IO
78 #if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
80 * TODO: Convert this to a clock driver exists that can give us the UART
83 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
86 #endif /* _ASM_CONFIG_H_ */