2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/config_mpc85xx.h>
15 #include <asm/config_mpc86xx.h>
21 #ifndef HWCONFIG_BUFFER_SIZE
22 #define HWCONFIG_BUFFER_SIZE 256
25 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
26 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
27 # ifndef CONFIG_HARD_SPI
28 # define CONFIG_HARD_SPI
33 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
35 #ifndef CONFIG_MAX_MEM_MAPPED
36 #if defined(CONFIG_E500) || \
37 defined(CONFIG_MPC86xx) || \
39 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
41 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
45 /* Check if boards need to enable FSL DMA engine for SDRAM init */
46 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
47 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
48 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
49 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
50 #define CONFIG_FSL_DMA
55 * Provide a default boot page translation virtual address that lines up with
56 * Freescale's default e500 reset page.
58 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
59 #ifndef CONFIG_BPTR_VIRT_ADDR
60 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000
64 /* Since so many PPC SOCs have a semi-common LBC, define this here */
65 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
66 defined(CONFIG_MPC83xx)
67 #if !defined(CONFIG_FSL_IFC)
68 #define CONFIG_FSL_LBC
72 /* The TSEC driver uses the PHYLIB infrastructure */
73 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
74 #include <config_phylib_all_drivers.h>
75 #endif /* TSEC_ENET */
77 /* The FMAN driver uses the PHYLIB infrastructure */
79 /* All PPC boards must swap IDE bytes */
80 #define CONFIG_IDE_SWAP_IO
82 #if defined(CONFIG_DM_SERIAL)
84 * TODO: Convert this to a clock driver exists that can give us the UART
87 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
90 #endif /* _ASM_CONFIG_H_ */