2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef _ASM_CONFIG_H_
22 #define _ASM_CONFIG_H_
25 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
26 #define CONFIG_SYS_BOOT_GET_CMDLINE
27 #define CONFIG_SYS_BOOT_GET_KBD
29 #ifndef CONFIG_MAX_MEM_MAPPED
30 #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
31 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
33 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
37 /* Check if boards need to enable FSL DMA engine for SDRAM init */
38 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
39 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
40 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
41 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
42 #define CONFIG_FSL_DMA
46 #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
47 defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
48 defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
49 #define CONFIG_MAX_CPUS 2
50 #elif defined(CONFIG_PPC_P2040)
51 #define CONFIG_MAX_CPUS 4
52 #elif defined(CONFIG_PPC_P3041)
53 #define CONFIG_MAX_CPUS 4
54 #elif defined(CONFIG_PPC_P4080)
55 #define CONFIG_MAX_CPUS 8
56 #elif defined(CONFIG_PPC_P5020)
57 #define CONFIG_MAX_CPUS 2
59 #define CONFIG_MAX_CPUS 1
63 * Provide a default boot page translation virtual address that lines up with
64 * Freescale's default e500 reset page.
66 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
67 #ifndef CONFIG_BPTR_VIRT_ADDR
68 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000
72 /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
73 #if defined(CONFIG_TSEC_ENET) && \
74 (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
75 defined(CONFIG_P1020) || defined(CONFIG_P1011))
80 * SEC (crypto unit) major compatible version determination
82 #if defined(CONFIG_FSL_CORENET) || \
83 defined(CONFIG_P1010) || defined(CONFIG_P1014)
84 #define CONFIG_SYS_FSL_SEC_COMPAT 4
85 #elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
86 #define CONFIG_SYS_FSL_SEC_COMPAT 2
89 /* Number of TLB CAM entries we have on FSL Book-E chips */
90 #if defined(CONFIG_E500MC)
91 #define CONFIG_SYS_NUM_TLBCAMS 64
92 #elif defined(CONFIG_E500)
93 #define CONFIG_SYS_NUM_TLBCAMS 16
96 /* Since so many PPC SOCs have a semi-common LBC, define this here */
97 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
98 defined(CONFIG_MPC83xx)
99 #define CONFIG_FSL_LBC
102 /* All PPC boards must swap IDE bytes */
103 #define CONFIG_IDE_SWAP_IO
105 #endif /* _ASM_CONFIG_H_ */