2 * MPC8xx Internal Memory Map
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * The I/O on the MPC860 is comprised of blocks of special registers
6 * and the dual port ram for the Communication Processor Module.
7 * Within this space are functional units such as the SIU, memory
8 * controller, system timers, and other control functions. It is
9 * a combination that I found difficult to separate into logical
10 * functional files.....but anyone else is welcome to try. -- Dan
15 /* System configuration registers.
17 typedef struct sys_conf {
33 /* PCMCIA configuration registers.
35 typedef struct pcmcia_conf {
63 /* Memory controller registers.
65 typedef struct mem_ctlr {
94 /* System Integration Timers.
96 typedef struct sys_int_timers {
115 #define TBSCR_TBIRQ_MASK ((ushort)0xff00)
116 #define TBSCR_REFA ((ushort)0x0080)
117 #define TBSCR_REFB ((ushort)0x0040)
118 #define TBSCR_REFAE ((ushort)0x0008)
119 #define TBSCR_REFBE ((ushort)0x0004)
120 #define TBSCR_TBF ((ushort)0x0002)
121 #define TBSCR_TBE ((ushort)0x0001)
123 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
124 #define RTCSC_SEC ((ushort)0x0080)
125 #define RTCSC_ALR ((ushort)0x0040)
126 #define RTCSC_38K ((ushort)0x0010)
127 #define RTCSC_SIE ((ushort)0x0008)
128 #define RTCSC_ALE ((ushort)0x0004)
129 #define RTCSC_RTF ((ushort)0x0002)
130 #define RTCSC_RTE ((ushort)0x0001)
132 #define PISCR_PIRQ_MASK ((ushort)0xff00)
133 #define PISCR_PS ((ushort)0x0080)
134 #define PISCR_PIE ((ushort)0x0004)
135 #define PISCR_PTF ((ushort)0x0002)
136 #define PISCR_PTE ((ushort)0x0001)
140 typedef struct clk_and_reset {
144 char res[0x74]; /* Reserved area */
147 /* System Integration Timers keys.
149 typedef struct sitk {
165 /* Clocks and reset keys.
167 typedef struct cark {
174 /* The key to unlock registers maintained by keep-alive power.
176 #define KAPWR_KEY ((unsigned int)0x55ccaa33)
178 /* Video interface. MPC823 Only.
180 typedef struct vid823 {
198 /* LCD interface. 823 Only.
228 /* DMA control/status registers.
230 typedef struct sdma_csr {
247 /* Communication Processor Module Interrupt Controller.
249 typedef struct cpm_ic {
258 /* Input/Output Port control/status registers.
260 typedef struct io_port {
280 /* Communication Processor Module Timers
282 typedef struct cpm_timers {
308 /* Finally, the Communication Processor stuff.....
310 typedef struct scc { /* Serial communication channels */
325 typedef struct smc { /* Serial management channels */
335 /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
336 * it fits within the address space.
340 uint fec_addr_low; /* lower 32 bits of station address */
341 ushort fec_addr_high; /* upper 16 bits of station address */
342 ushort res1; /* reserved */
343 uint fec_hash_table_high; /* upper 32-bits of hash table */
344 uint fec_hash_table_low; /* lower 32-bits of hash table */
345 uint fec_r_des_start; /* beginning of Rx descriptor ring */
346 uint fec_x_des_start; /* beginning of Tx descriptor ring */
347 uint fec_r_buff_size; /* Rx buffer size */
348 uint res2[9]; /* reserved */
349 uint fec_ecntrl; /* ethernet control register */
350 uint fec_ievent; /* interrupt event register */
351 uint fec_imask; /* interrupt mask register */
352 uint fec_ivec; /* interrupt level and vector status */
353 uint fec_r_des_active; /* Rx ring updated flag */
354 uint fec_x_des_active; /* Tx ring updated flag */
355 uint res3[10]; /* reserved */
356 uint fec_mii_data; /* MII data register */
357 uint fec_mii_speed; /* MII speed control register */
358 uint res4[17]; /* reserved */
359 uint fec_r_bound; /* end of RAM (read-only) */
360 uint fec_r_fstart; /* Rx FIFO start address */
361 uint res5[6]; /* reserved */
362 uint fec_x_fstart; /* Tx FIFO start address */
363 uint res6[17]; /* reserved */
364 uint fec_fun_code; /* fec SDMA function code */
365 uint res7[3]; /* reserved */
366 uint fec_r_cntrl; /* Rx control register */
367 uint fec_r_hash; /* Rx hash register */
368 uint res8[14]; /* reserved */
369 uint fec_x_cntrl; /* Tx control register */
370 uint res9[0x1e]; /* reserved */
373 /* The FEC and LCD color map share the same address space....
374 * I guess we will never see an 823T :-).
378 u_char fl_un_cmap[0x200];
381 typedef struct comm_proc {
382 /* General control and status registers.
400 /* Baud rate generators.
407 /* Serial Communication Channels.
411 /* Serial Management Channels.
415 /* Serial Peripheral Interface.
426 /* Parallel Interface Port.
438 /* Port E - MPC87x/88x only.
446 /* Communications Processor Timing Register -
447 Contains RMII Timing for the FECs on MPC87x/88x only.
451 /* Serial Interface and Time Slot Assignment.
463 /* 256 bytes of MPC823 video controller RAM array.
465 u_char cp_vcram[0x100];
466 u_char cp_siram[0x200];
468 /* The fast ethernet controller is not really part of the CPM,
469 * but it resides in the address space.
470 * The LCD color map is also here.
473 #define cp_fec fl_un.fl_un_fec
474 #define lcd_cmap fl_un.fl_un_cmap
477 /* The MPC885 family has a second FEC here */
479 #define cp_fec1 cp_fec /* consistency macro */
481 /* Dual Ported RAM follows.
482 * There are many different formats for this memory area
483 * depending upon the devices used and options chosen.
484 * Some processors don't have all of it populated.
486 u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
490 u_char cp_dparam[0x400];
491 u16 cp_dparam16[0x200];
495 /* Internal memory map.
497 typedef struct immap {
498 sysconf8xx_t im_siu_conf; /* SIU Configuration */
499 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
500 memctl8xx_t im_memctl; /* Memory Controller */
501 sit8xx_t im_sit; /* System integration timers */
502 car8xx_t im_clkrst; /* Clocks and reset */
503 sitk8xx_t im_sitk; /* Sys int timer keys */
504 cark8xx_t im_clkrstk; /* Clocks and reset keys */
505 vid823_t im_vid; /* Video (823 only) */
506 lcd823_t im_lcd; /* LCD (823 only) */
507 i2c8xx_t im_i2c; /* I2C control/status */
508 sdma8xx_t im_sdma; /* SDMA control/status */
509 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
510 iop8xx_t im_ioport; /* IO Port control/status */
511 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
512 cpm8xx_t im_cpm; /* Communication processor */
515 #endif /* __IMMAP_8XX__ */