arch/powerpc/dts/t4240.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * T4240 Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2013 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e6500_power_isa.dtsi"
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: PowerPC,e6500@0 {
  23                         device_type = "cpu";
  24                         reg = <0 1>;
  25                         fsl,portid-mapping = <0x80000000>;
  26                 };
  27                 cpu1: PowerPC,e6500@2 {
  28                         device_type = "cpu";
  29                         reg = <2 3>;
  30                         fsl,portid-mapping = <0x80000000>;
  31                 };
  32                 cpu2: PowerPC,e6500@4 {
  33                         device_type = "cpu";
  34                         reg = <4 5>;
  35                         fsl,portid-mapping = <0x80000000>;
  36                 };
  37                 cpu3: PowerPC,e6500@6 {
  38                         device_type = "cpu";
  39                         reg = <6 7>;
  40                         fsl,portid-mapping = <0x80000000>;
  41                 };
  42                 cpu4: PowerPC,e6500@8 {
  43                         device_type = "cpu";
  44                         reg = <8 9>;
  45                         fsl,portid-mapping = <0x80000000>;
  46                 };
  47                 cpu5: PowerPC,e6500@10 {
  48                         device_type = "cpu";
  49                         reg = <10 11>;
  50                         fsl,portid-mapping = <0x80000000>;
  51                 };
  52                 cpu6: PowerPC,e6500@12 {
  53                         device_type = "cpu";
  54                         reg = <12 13>;
  55                         fsl,portid-mapping = <0x80000000>;
  56                 };
  57                 cpu7: PowerPC,e6500@14 {
  58                         device_type = "cpu";
  59                         reg = <14 15>;
  60                         fsl,portid-mapping = <0x80000000>;
  61                 };
  62                 cpu8: PowerPC,e6500@16 {
  63                         device_type = "cpu";
  64                         reg = <16 17>;
  65                         fsl,portid-mapping = <0x80000000>;
  66                 };
  67                 cpu9: PowerPC,e6500@18 {
  68                         device_type = "cpu";
  69                         reg = <18 19>;
  70                         fsl,portid-mapping = <0x80000000>;
  71                 };
  72                 cpu10: PowerPC,e6500@20 {
  73                         device_type = "cpu";
  74                         reg = <20 21>;
  75                         fsl,portid-mapping = <0x80000000>;
  76                 };
  77                 cpu11: PowerPC,e6500@22 {
  78                         device_type = "cpu";
  79                         reg = <22 23>;
  80                         fsl,portid-mapping = <0x80000000>;
  81                 };
  82         };
  83
  84         soc: soc@ffe000000 {
  85                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  86                 reg = <0xf 0xfe000000 0 0x00001000>;
  87                 #address-cells = <1>;
  88                 #size-cells = <1>;
  89                 device_type = "soc";
  90                 compatible = "simple-bus";
  91
  92                 mpic: pic@40000 {
  93                         interrupt-controller;
  94                         #address-cells = <0>;
  95                         #interrupt-cells = <4>;
  96                         reg = <0x40000 0x40000>;
  97                         compatible = "fsl,mpic";
  98                         device_type = "open-pic";
  99                         clock-frequency = <0x0>;
 100                 };
 101         };
 102
 103         pcie@ffe240000 {
 104                 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
 105                 reg = <0xf 0xfe240000 0x0 0x4000>;   /* registers */
 106                 law_trgt_if = <0>;
 107                 #address-cells = <3>;
 108                 #size-cells = <2>;
 109                 device_type = "pci";
 110                 bus-range = <0x0 0xff>;
 111                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
 112                           0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
 113         };
 114
 115         pcie@ffe250000 {
 116                 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
 117                 reg = <0xf 0xfe250000 0x0 0x4000>;   /* registers */
 118                 law_trgt_if = <1>;
 119                 #address-cells = <3>;
 120                 #size-cells = <2>;
 121                 device_type = "pci";
 122                 bus-range = <0x0 0xff>;
 123                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
 124                           0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
 125         };
 126
 127         pcie@ffe260000 {
 128                 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
 129                 reg = <0xf 0xfe260000 0x0 0x4000>;   /* registers */
 130                 law_trgt_if = <2>;
 131                 #address-cells = <3>;
 132                 #size-cells = <2>;
 133                 device_type = "pci";
 134                 bus-range = <0x0 0xff>;
 135                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
 136                           0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
 137         };
 138
 139         pcie@ffe270000 {
 140                 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
 141                 reg = <0xf 0xfe270000 0x0 0x4000>;   /* registers */
 142                 law_trgt_if = <3>;
 143                 #address-cells = <3>;
 144                 #size-cells = <2>;
 145                 device_type = "pci";
 146                 bus-range = <0x0 0xff>;
 147                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
 148                           0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
 149         };
 150 };