1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * T4240 Silicon/SoC Device Tree Source (pre include)
5 * Copyright 2013 Freescale Semiconductor Inc.
11 /include/ "e6500_power_isa.dtsi"
16 interrupt-parent = <&mpic>;
22 cpu0: PowerPC,e6500@0 {
25 fsl,portid-mapping = <0x80000000>;
27 cpu1: PowerPC,e6500@2 {
30 fsl,portid-mapping = <0x80000000>;
32 cpu2: PowerPC,e6500@4 {
35 fsl,portid-mapping = <0x80000000>;
37 cpu3: PowerPC,e6500@6 {
40 fsl,portid-mapping = <0x80000000>;
42 cpu4: PowerPC,e6500@8 {
45 fsl,portid-mapping = <0x80000000>;
47 cpu5: PowerPC,e6500@10 {
50 fsl,portid-mapping = <0x80000000>;
52 cpu6: PowerPC,e6500@12 {
55 fsl,portid-mapping = <0x80000000>;
57 cpu7: PowerPC,e6500@14 {
60 fsl,portid-mapping = <0x80000000>;
62 cpu8: PowerPC,e6500@16 {
65 fsl,portid-mapping = <0x80000000>;
67 cpu9: PowerPC,e6500@18 {
70 fsl,portid-mapping = <0x80000000>;
72 cpu10: PowerPC,e6500@20 {
75 fsl,portid-mapping = <0x80000000>;
77 cpu11: PowerPC,e6500@22 {
80 fsl,portid-mapping = <0x80000000>;
85 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
86 reg = <0xf 0xfe000000 0 0x00001000>;
90 compatible = "simple-bus";
95 #interrupt-cells = <4>;
96 reg = <0x40000 0x40000>;
97 compatible = "fsl,mpic";
98 device_type = "open-pic";
99 clock-frequency = <0x0>;
103 compatible = "fsl,pq-sata-v2";
104 reg = <0x220000 0x1000>;
105 interrupts = <68 0x2 0 0>;
106 sata-offset = <0x1000>;
113 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
114 reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
116 #address-cells = <3>;
119 bus-range = <0x0 0xff>;
120 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
121 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
125 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
126 reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */
128 #address-cells = <3>;
131 bus-range = <0x0 0xff>;
132 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
133 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
137 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
138 reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */
140 #address-cells = <3>;
143 bus-range = <0x0 0xff>;
144 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
145 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
149 compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
150 reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */
152 #address-cells = <3>;
155 bus-range = <0x0 0xff>;
156 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
157 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */