1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
5 * Copyright 2013 Freescale Semiconductor Inc.
11 /include/ "e6500_power_isa.dtsi"
16 interrupt-parent = <&mpic>;
22 cpu0: PowerPC,e6500@0 {
25 fsl,portid-mapping = <0x80000000>;
27 cpu1: PowerPC,e6500@2 {
30 fsl,portid-mapping = <0x80000000>;
32 cpu2: PowerPC,e6500@4 {
35 fsl,portid-mapping = <0x80000000>;
37 cpu3: PowerPC,e6500@6 {
40 fsl,portid-mapping = <0x80000000>;
45 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
46 reg = <0xf 0xfe000000 0 0x00001000>;
50 compatible = "simple-bus";
55 #interrupt-cells = <4>;
56 reg = <0x40000 0x40000>;
57 compatible = "fsl,mpic";
58 device_type = "open-pic";
59 clock-frequency = <0x0>;
63 compatible = "fsl,esdhc";
64 reg = <0x114000 0x1000>;
65 interrupts = <48 2 0 0>;
66 clock-frequency = <0>;
69 voltage-ranges = <1800 1800 3300 3300>;
73 compatible = "fsl-usb2-mph";
74 reg = <0x210000 0x1000>;
77 interrupts = <44 0x2 0 0>;
82 compatible = "fsl-usb2-dr";
83 reg = <0x211000 0x1000>;
86 interrupts = <45 0x2 0 0>;
92 compatible = "fsl,pq-sata-v2";
93 reg = <0x220000 0x1000>;
94 interrupts = <68 0x2 0 0>;
95 sata-offset = <0x1000>;
102 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
103 reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
105 #address-cells = <3>;
108 bus-range = <0x0 0xff>;
109 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
110 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
114 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
115 reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
117 #address-cells = <3>;
120 bus-range = <0x0 0xff>;
121 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
122 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
126 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
127 reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
129 #address-cells = <3>;
132 bus-range = <0x0 0xff>;
133 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
134 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
138 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
139 reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
141 #address-cells = <3>;
144 bus-range = <0x0 0xff>;
145 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
146 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */