arch/powerpc/dts/t104x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * T104X Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2013 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e5500_power_isa.dtsi"
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: PowerPC,e5500@0 {
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         #cooling-cells = <2>;
  26                 };
  27                 cpu1: PowerPC,e5500@1 {
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         #cooling-cells = <2>;
  31                 };
  32                 cpu2: PowerPC,e5500@2 {
  33                         device_type = "cpu";
  34                         reg = <2>;
  35                         #cooling-cells = <2>;
  36                 };
  37                 cpu3: PowerPC,e5500@3 {
  38                         device_type = "cpu";
  39                         reg = <3>;
  40                         #cooling-cells = <2>;
  41                 };
  42         };
  43
  44         soc: soc@ffe000000 {
  45                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  46                 reg = <0xf 0xfe000000 0 0x00001000>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 device_type = "soc";
  50                 compatible = "simple-bus";
  51
  52                 mpic: pic@40000 {
  53                         interrupt-controller;
  54                         #address-cells = <0>;
  55                         #interrupt-cells = <4>;
  56                         reg = <0x40000 0x40000>;
  57                         compatible = "fsl,mpic", "chrp,open-pic";
  58                         device_type = "open-pic";
  59                         clock-frequency = <0x0>;
  60                 };
  61
  62                 sata: sata@220000 {
  63                         compatible = "fsl,pq-sata-v2";
  64                         reg = <0x220000 0x1000>;
  65                         interrupts = <68 0x2 0 0>;
  66                         sata-offset = <0x1000>;
  67                         sata-number = <2>;
  68                         sata-fpdma = <0>;
  69                 };
  70         };
  71
  72         pcie@ffe240000 {
  73                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
  74                 reg = <0xf 0xfe240000 0x0 0x1000>;   /* registers */
  75                 law_trgt_if = <0>;
  76                 #address-cells = <3>;
  77                 #size-cells = <2>;
  78                 device_type = "pci";
  79                 bus-range = <0x0 0xff>;
  80                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
  81                           0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
  82         };
  83
  84         pcie@ffe250000 {
  85                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
  86                 reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
  87                 law_trgt_if = <1>;
  88                 #address-cells = <3>;
  89                 #size-cells = <2>;
  90                 device_type = "pci";
  91                 bus-range = <0x0 0xff>;
  92                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
  93                           0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
  94         };
  95
  96         pcie@ffe260000 {
  97                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
  98                 reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
  99                 law_trgt_if = <2>;
 100                 #address-cells = <3>;
 101                 #size-cells = <2>;
 102                 device_type = "pci";
 103                 bus-range = <0x0 0xff>;
 104                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
 105                           0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
 106         };
 107
 108         pcie@ffe270000 {
 109                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
 110                 reg = <0xf 0xfe270000 0x0 0x1000>;   /* registers */
 111                 law_trgt_if = <3>;
 112                 #address-cells = <3>;
 113                 #size-cells = <2>;
 114                 device_type = "pci";
 115                 bus-range = <0x0 0xff>;
 116                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
 117                           0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
 118         };
 119 };