arch/powerpc/dts/t104x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * T104X Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2013 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e5500_power_isa.dtsi"
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: PowerPC,e5500@0 {
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         #cooling-cells = <2>;
  26                 };
  27                 cpu1: PowerPC,e5500@1 {
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         #cooling-cells = <2>;
  31                 };
  32                 cpu2: PowerPC,e5500@2 {
  33                         device_type = "cpu";
  34                         reg = <2>;
  35                         #cooling-cells = <2>;
  36                 };
  37                 cpu3: PowerPC,e5500@3 {
  38                         device_type = "cpu";
  39                         reg = <3>;
  40                         #cooling-cells = <2>;
  41                 };
  42         };
  43
  44         soc: soc@ffe000000 {
  45                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  46                 reg = <0xf 0xfe000000 0 0x00001000>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 device_type = "soc";
  50                 compatible = "simple-bus";
  51
  52                 mpic: pic@40000 {
  53                         interrupt-controller;
  54                         #address-cells = <0>;
  55                         #interrupt-cells = <4>;
  56                         reg = <0x40000 0x40000>;
  57                         compatible = "fsl,mpic", "chrp,open-pic";
  58                         device_type = "open-pic";
  59                         clock-frequency = <0x0>;
  60                 };
  61         };
  62
  63         pcie@ffe240000 {
  64                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
  65                 reg = <0xf 0xfe240000 0x0 0x1000>;   /* registers */
  66                 law_trgt_if = <0>;
  67                 #address-cells = <3>;
  68                 #size-cells = <2>;
  69                 device_type = "pci";
  70                 bus-range = <0x0 0xff>;
  71                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
  72                           0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
  73         };
  74
  75         pcie@ffe250000 {
  76                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
  77                 reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
  78                 law_trgt_if = <1>;
  79                 #address-cells = <3>;
  80                 #size-cells = <2>;
  81                 device_type = "pci";
  82                 bus-range = <0x0 0xff>;
  83                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
  84                           0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
  85         };
  86
  87         pcie@ffe260000 {
  88                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
  89                 reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
  90                 law_trgt_if = <2>;
  91                 #address-cells = <3>;
  92                 #size-cells = <2>;
  93                 device_type = "pci";
  94                 bus-range = <0x0 0xff>;
  95                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
  96                           0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
  97         };
  98
  99         pcie@ffe270000 {
 100                 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
 101                 reg = <0xf 0xfe270000 0x0 0x1000>;   /* registers */
 102                 law_trgt_if = <3>;
 103                 #address-cells = <3>;
 104                 #size-cells = <2>;
 105                 device_type = "pci";
 106                 bus-range = <0x0 0xff>;
 107                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
 108                           0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
 109         };
 110 };