1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * T104X Silicon/SoC Device Tree Source (pre include)
5 * Copyright 2013 Freescale Semiconductor Inc.
11 /include/ "e5500_power_isa.dtsi"
16 interrupt-parent = <&mpic>;
22 cpu0: PowerPC,e5500@0 {
27 cpu1: PowerPC,e5500@1 {
32 cpu2: PowerPC,e5500@2 {
37 cpu3: PowerPC,e5500@3 {
45 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
46 reg = <0xf 0xfe000000 0 0x00001000>;
50 compatible = "simple-bus";
55 #interrupt-cells = <4>;
56 reg = <0x40000 0x40000>;
57 compatible = "fsl,mpic", "chrp,open-pic";
58 device_type = "open-pic";
59 clock-frequency = <0x0>;
64 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
65 reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
70 bus-range = <0x0 0xff>;
71 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
72 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
76 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
77 reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
82 bus-range = <0x0 0xff>;
83 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
84 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
88 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
89 reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
94 bus-range = <0x0 0xff>;
95 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
96 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
100 compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
101 reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
103 #address-cells = <3>;
106 bus-range = <0x0 0xff>;
107 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
108 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */