1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * T102X Silicon/SoC Device Tree Source (pre include)
5 * Copyright 2013 Freescale Semiconductor Inc.
11 /include/ "e5500_power_isa.dtsi"
16 interrupt-parent = <&mpic>;
22 cpu0: PowerPC,e5500@0 {
27 cpu1: PowerPC,e5500@1 {
35 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
36 reg = <0xf 0xfe000000 0 0x00001000>;
40 compatible = "simple-bus";
45 #interrupt-cells = <4>;
46 reg = <0x40000 0x40000>;
47 compatible = "fsl,mpic", "chrp,open-pic";
48 device_type = "open-pic";
49 clock-frequency = <0x0>;
53 compatible = "fsl,pq-sata-v2";
54 reg = <0x220000 0x1000>;
55 interrupts = <68 0x2 0 0>;
56 sata-offset = <0x1000>;
62 compatible = "fsl,esdhc";
63 reg = <0x114000 0x1000>;
64 clock-frequency = <0>;
69 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
70 reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
75 bus-range = <0x0 0xff>;
76 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
77 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
81 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
82 reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
87 bus-range = <0x0 0xff>;
88 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
89 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
93 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
94 reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
99 bus-range = <0x0 0xff>;
100 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
101 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */