1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * T102X Silicon/SoC Device Tree Source (pre include)
5 * Copyright 2013 Freescale Semiconductor Inc.
11 /include/ "e5500_power_isa.dtsi"
16 interrupt-parent = <&mpic>;
22 cpu0: PowerPC,e5500@0 {
27 cpu1: PowerPC,e5500@1 {
35 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
36 reg = <0xf 0xfe000000 0 0x00001000>;
40 compatible = "simple-bus";
45 #interrupt-cells = <4>;
46 reg = <0x40000 0x40000>;
47 compatible = "fsl,mpic", "chrp,open-pic";
48 device_type = "open-pic";
49 clock-frequency = <0x0>;
54 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
55 reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
60 bus-range = <0x0 0xff>;
61 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
62 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
66 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
67 reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
72 bus-range = <0x0 0xff>;
73 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
74 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
78 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
79 reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
84 bus-range = <0x0 0xff>;
85 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
86 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */