arch/powerpc/dts/p4080.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e500mc_power_isa.dtsi"
  12
  13 / {
  14         compatible = "fsl,P4080";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&mpic>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: PowerPC,e500mc@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         fsl,portid-mapping = <0x80000000>;
  27                 };
  28                 cpu1: PowerPC,e500mc@1 {
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         fsl,portid-mapping = <0x40000000>;
  32                 };
  33                 cpu2: PowerPC,e500mc@2 {
  34                         device_type = "cpu";
  35                         reg = <2>;
  36                         fsl,portid-mapping = <0x20000000>;
  37                 };
  38                 cpu3: PowerPC,e500mc@3 {
  39                         device_type = "cpu";
  40                         reg = <3>;
  41                         fsl,portid-mapping = <0x10000000>;
  42                 };
  43                 cpu4: PowerPC,e500mc@4 {
  44                         device_type = "cpu";
  45                         reg = <4>;
  46                         fsl,portid-mapping = <0x08000000>;
  47                 };
  48                 cpu5: PowerPC,e500mc@5 {
  49                         device_type = "cpu";
  50                         reg = <5>;
  51                         fsl,portid-mapping = <0x04000000>;
  52                 };
  53                 cpu6: PowerPC,e500mc@6 {
  54                         device_type = "cpu";
  55                         reg = <6>;
  56                         fsl,portid-mapping = <0x02000000>;
  57                 };
  58                 cpu7: PowerPC,e500mc@7 {
  59                         device_type = "cpu";
  60                         reg = <7>;
  61                         fsl,portid-mapping = <0x01000000>;
  62                 };
  63         };
  64
  65         soc: soc@ffe000000 {
  66                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  67                 reg = <0xf 0xfe000000 0 0x00001000>;
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 device_type = "soc";
  71                 compatible = "simple-bus";
  72
  73                 mpic: pic@40000 {
  74                         interrupt-controller;
  75                         #address-cells = <0>;
  76                         #interrupt-cells = <4>;
  77                         reg = <0x40000 0x40000>;
  78                         compatible = "fsl,mpic", "chrp,open-pic";
  79                         device_type = "open-pic";
  80                         clock-frequency = <0x0>;
  81                 };
  82         };
  83 };