arch/powerpc/dts/p2041rdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P2041RDB Device Tree Source
   4  *
   5  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /include/ "p2041.dtsi"
  10
  11 / {
  12         model = "fsl,P2041RDB";
  13         compatible = "fsl,P2041RDB";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         aliases {
  19                 phy_rgmii_0 = &phy_rgmii_0;
  20                 phy_rgmii_1 = &phy_rgmii_1;
  21                 phy_sgmii_2 = &phy_sgmii_2;
  22                 phy_sgmii_3 = &phy_sgmii_3;
  23                 phy_sgmii_4 = &phy_sgmii_4;
  24                 phy_sgmii_1c = &phy_sgmii_1c;
  25                 phy_sgmii_1d = &phy_sgmii_1d;
  26                 phy_sgmii_1e = &phy_sgmii_1e;
  27                 phy_sgmii_1f = &phy_sgmii_1f;
  28                 phy_xgmii_2 = &phy_xgmii_2;
  29         };
  30
  31         soc: soc@ffe000000 {
  32                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  33                 reg = <0xf 0xfe000000 0 0x00001000>;
  34
  35                 fman@400000 {
  36                         ethernet@e0000 {
  37                                 phy-handle = <&phy_sgmii_2>;
  38                                 phy-connection-type = "sgmii";
  39                         };
  40
  41                         mdio@e1120 {
  42                                 phy_rgmii_0: ethernet-phy@0 {
  43                                         reg = <0x0>;
  44                                 };
  45
  46                                 phy_rgmii_1: ethernet-phy@1 {
  47                                         reg = <0x1>;
  48                                 };
  49
  50                                 phy_sgmii_2: ethernet-phy@2 {
  51                                         reg = <0x2>;
  52                                 };
  53
  54                                 phy_sgmii_3: ethernet-phy@3 {
  55                                         reg = <0x3>;
  56                                 };
  57
  58                                 phy_sgmii_4: ethernet-phy@4 {
  59                                         reg = <0x4>;
  60                                 };
  61
  62                                 phy_sgmii_1c: ethernet-phy@1c {
  63                                         reg = <0x1c>;
  64                                 };
  65
  66                                 phy_sgmii_1d: ethernet-phy@1d {
  67                                         reg = <0x1d>;
  68                                 };
  69
  70                                 phy_sgmii_1e: ethernet-phy@1e {
  71                                         reg = <0x1e>;
  72                                 };
  73
  74                                 phy_sgmii_1f: ethernet-phy@1f {
  75                                         reg = <0x1f>;
  76                                 };
  77                         };
  78
  79                         ethernet@e2000 {
  80                                 phy-handle = <&phy_sgmii_3>;
  81                                 phy-connection-type = "sgmii";
  82                         };
  83
  84                         ethernet@e4000 {
  85                                 phy-handle = <&phy_sgmii_4>;
  86                                 phy-connection-type = "sgmii";
  87                         };
  88
  89                         ethernet@e6000 {
  90                                 phy-handle = <&phy_rgmii_1>;
  91                                 phy-connection-type = "rgmii";
  92                         };
  93
  94                         ethernet@e8000 {
  95                                 phy-handle = <&phy_rgmii_0>;
  96                                 phy-connection-type = "rgmii";
  97                         };
  98
  99                         ethernet@f0000 {
 100                                 phy-handle = <&phy_xgmii_2>;
 101                                 phy-connection-type = "xgmii";
 102                         };
 103
 104                         mdio@f1000 {
 105                                 phy_xgmii_2: ethernet-phy@0 {
 106                                         compatible = "ethernet-phy-ieee802.3-c45";
 107                                         reg = <0x0>;
 108                                 };
 109                         };
 110                 };
 111         };
 112 };
 113
 114 /include/ "p2041si-post.dtsi"