arch/powerpc/dts/p2041.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P2041 Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e500mc_power_isa.dtsi"
  12
  13 / {
  14         compatible = "fsl,P2041";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&mpic>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: PowerPC,e500mc@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         fsl,portid-mapping = <0x80000000>;
  27                 };
  28                 cpu1: PowerPC,e500mc@1 {
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         fsl,portid-mapping = <0x40000000>;
  32                 };
  33                 cpu2: PowerPC,e500mc@2 {
  34                         device_type = "cpu";
  35                         reg = <2>;
  36                         fsl,portid-mapping = <0x20000000>;
  37                 };
  38                 cpu3: PowerPC,e500mc@3 {
  39                         device_type = "cpu";
  40                         reg = <3>;
  41                         fsl,portid-mapping = <0x10000000>;
  42                 };
  43         };
  44
  45         soc: soc@ffe000000 {
  46                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  47                 reg = <0xf 0xfe000000 0 0x00001000>;
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 device_type = "soc";
  51                 compatible = "simple-bus";
  52
  53                 mpic: pic@40000 {
  54                         interrupt-controller;
  55                         #address-cells = <0>;
  56                         #interrupt-cells = <4>;
  57                         reg = <0x40000 0x40000>;
  58                         compatible = "fsl,mpic", "chrp,open-pic";
  59                         device_type = "open-pic";
  60                         clock-frequency = <0x0>;
  61                 };
  62         };
  63
  64         pcie@ffe200000 {
  65                 compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
  66                 reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
  67                 law_trgt_if = <0>;
  68                 #address-cells = <3>;
  69                 #size-cells = <2>;
  70                 device_type = "pci";
  71                 bus-range = <0x0 0xff>;
  72                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
  73                           0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
  74         };
  75
  76         pcie@ffe201000 {
  77                 compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
  78                 reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
  79                 law_trgt_if = <1>;
  80                 #address-cells = <3>;
  81                 #size-cells = <2>;
  82                 device_type = "pci";
  83                 bus-range = <0x0 0xff>;
  84                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
  85                           0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
  86         };
  87
  88         pcie@ffe202000 {
  89                 compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
  90                 reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
  91                 law_trgt_if = <2>;
  92                 #address-cells = <3>;
  93                 #size-cells = <2>;
  94                 device_type = "pci";
  95                 bus-range = <0x0 0xff>;
  96                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
  97                           0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
  98         };
  99 };