1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * P1020 Silicon/SoC Device Tree Source (post include)
5 * Copyright 2013 Freescale Semiconductor Inc.
13 compatible = "fsl,p1020-immr", "simple-bus";
14 bus-frequency = <0x0>;
19 #interrupt-cells = <4>;
20 reg = <0x40000 0x40000>;
21 compatible = "fsl,mpic";
22 device_type = "open-pic";
25 last-interrupt-source = <255>;
29 compatible = "fsl,esdhc";
30 reg = <0x2e000 0x1000>;
31 /* Filled in by U-Boot */
32 clock-frequency = <0>;
36 /* PCIe controller base address 0x9000 */
38 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
43 bus-range = <0x0 0xff>;
46 /* PCIe controller base address 0xa000 */
48 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
53 bus-range = <0x0 0xff>;