2 * Basic platform for gdsys mpc8308 based devices
5 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
8 * Copyright 2009 Freescale Semiconductor Inc.
9 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
19 #include <dt-bindings/memory/mpc83xx-sdram.h>
22 compatible = "fsl,mpc8308rdb";
33 device_type = "memory";
43 d-cache-line-size = <32>;
44 i-cache-line-size = <32>;
45 d-cache-size = <16384>;
46 i-cache-size = <16384>;
47 timebase-frequency = <0>; // from bootloader
48 bus-frequency = <0>; // from bootloader
49 clock-frequency = <0>; // from bootloader
53 board_lbc: localbus@e0005000 {
56 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
57 reg = <0xe0005000 0x1000>;
58 interrupts = <77 0x8>;
59 interrupt-parent = <&ipic>;
62 board_soc: immr@e0000000 {
66 compatible = "fsl,mpc8308-immr", "simple-bus";
67 ranges = <0 0xe0000000 0x00100000>;
68 reg = <0xe0000000 0x00000200>;
72 device_type = "watchdog";
73 compatible = "mpc83xx_wdt";
80 compatible = "fsl,mpc83xx-mem-controller";
81 reg = <0x2000 0x1000>;
82 device_type = "memory";
84 driver_software_override = <DSO_ENABLE>;
85 p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
86 n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
87 odt_termination_value = <ODT_TERMINATION_150_OHM>;
88 ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
90 clock_adjust = <CLOCK_ADJUST_05>;
96 active_powerdown_exit = <2>;
97 precharge_powerdown_exit = <6>;
98 odt_powerdown_exit = <8>;
99 mode_reg_set_cycle = <2>;
101 precharge_to_activate = <2>;
102 activate_to_precharge = <6>;
103 activate_to_readwrite = <2>;
104 mcas_latency = <CASLAT_40>;
105 refresh_recovery = <17>;
106 last_data_to_precharge = <2>;
107 activate_to_activate = <2>;
108 last_write_data_to_read = <2>;
110 additive_latency = <0>;
111 mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
113 read_to_precharge = <2>;
114 write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
115 minimum_cke_pulse_width = <3>;
116 four_activates_window = <5>;
118 self_refresh = <SREN_ENABLE>;
119 sdram_type = <TYPE_DDR2>;
120 databus_width = <DATA_BUS_WIDTH_32>;
122 force_self_refresh = <MODE_NORMAL>;
123 dll_reset = <DLL_RESET_ENABLE>;
124 dqs_config = <DQS_TRUE>;
125 odt_config = <ODT_ASSERT_READS>;
126 posted_refreshes = <1>;
128 refresh_interval = <2084>;
129 precharge_interval = <256>;
135 reg = <0x0 0x0 0x8000000>;
136 compatible = "nanya,nt5tu64m16hg";
138 odt_rd_cfg = <ODT_RD_NEVER>;
139 odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
147 #address-cells = <1>;
150 compatible = "fsl-i2c";
151 reg = <0x3000 0x100>;
152 interrupts = <14 0x8>;
153 interrupt-parent = <&ipic>;
158 #address-cells = <1>;
160 compatible = "fsl-i2c";
161 reg = <0x3100 0x100>;
162 interrupts = <15 0x8>;
163 interrupt-parent = <&ipic>;
169 #address-cells = <1>;
172 compatible = "fsl,spi";
173 reg = <0x7000 0x1000>;
174 interrupts = <16 0x8>;
175 interrupt-parent = <&ipic>;
180 compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
181 reg = <0x2e000 0x1000>;
182 interrupts = <42 0x8>;
183 interrupt-parent = <&ipic>;
185 /* Filled in by U-Boot */
186 clock-frequency = <0>;
189 serial0: serial@4500 {
191 device_type = "serial";
192 compatible = "fsl,ns16550", "ns16550";
193 reg = <0x4500 0x100>;
194 clock-frequency = <133333333>;
195 interrupts = <9 0x8>;
196 interrupt-parent = <&ipic>;
199 serial1: serial@4600 {
201 device_type = "serial";
202 compatible = "fsl,ns16550", "ns16550";
203 reg = <0x4600 0x100>;
204 clock-frequency = <133333333>;
205 interrupts = <10 0x8>;
206 interrupt-parent = <&ipic>;
211 device_type = "gpio";
212 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
214 interrupts = <74 0x8>;
215 interrupt-parent = <&ipic>;
220 * interrupts cell = <intr #, sense>
221 * sense values match linux IORESOURCE_IRQ_* defines:
222 * sense == 8: Level, low assertion
223 * sense == 2: Edge, high-to-low change
225 ipic: interrupt-controller@700 {
226 compatible = "fsl,ipic";
227 interrupt-controller;
228 #address-cells = <0>;
229 #interrupt-cells = <2>;
231 device_type = "ipic";
235 compatible = "fsl,ipic-msi";
237 msi-available-ranges = <0x0 0x100>;
238 interrupts = < 0x43 0x8
246 interrupt-parent = < &ipic >;
250 compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
251 reg = <0x2c000 0x1800>;
254 interrupt-parent = < &ipic >;
257 enet0: ethernet@24000 {
258 #address-cells = <1>;
260 ranges = <0x0 0x24000 0x1000>;
263 device_type = "network";
265 compatible = "gianfar", "fsl,tsec";
266 reg = <0x24000 0x1000>;
267 local-mac-address = [ 00 00 00 00 00 00 ];
268 interrupts = <32 0x8 33 0x8 34 0x8>;
269 interrupt-parent = <&ipic>;
270 tbi-handle = < &tbi0 >;
271 phy-handle = < &phy1 >;
275 #address-cells = <1>;
277 compatible = "fsl,gianfar-mdio";
279 phy1: ethernet-phy@1 {
282 phy2: ethernet-phy@0 {
284 device_type = "ethernet-phy";
288 device_type = "tbi-phy";
293 enet1: ethernet@25000 {
294 #address-cells = <1>;
297 device_type = "network";
299 compatible = "gianfar", "fsl,tsec";
300 reg = <0x25000 0x1000>;
301 ranges = <0x0 0x25000 0x1000>;
302 local-mac-address = [ 00 00 00 00 00 00 ];
303 interrupts = <35 0x8 36 0x8 37 0x8>;
304 interrupt-parent = <&ipic>;
305 phy-handle = < &phy2 >;
309 #address-cells = <1>;
311 compatible = "fsl,gianfar-tbi";
315 device_type = "tbi-phy";
321 pci0: pcie@e0009000 {
322 #address-cells = <3>;
324 #interrupt-cells = <1>;
326 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
327 reg = <0xe0009000 0x00001000
328 0xb0000000 0x01000000>;
329 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
330 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
332 interrupt-map-mask = <0xf800 0 0 7>;
333 interrupt-map = <0 0 0 1 &ipic 1 8
337 interrupts = <0x1 0x8>;
338 interrupt-parent = <&ipic>;
339 clock-frequency = <0>;
342 #address-cells = <3>;
346 ranges = <0x02000000 0 0xa0000000
347 0x02000000 0 0xa0000000
349 0x01000000 0 0x00000000
350 0x01000000 0 0x00000000