2 * Gazerbeam CON Device Tree Source
5 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include "gdsys/mpc8308.dtsi"
15 /include/ "gdsys/gazerbeam-base.dtsi"
17 /include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
18 /include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
19 /include/ "gdsys/soc/lbc/gazerbeam.dtsi"
20 /include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
23 FPGA0:iocon_uart@1,0 {
24 reg = <0x1 0x0 0x100000>;
26 interrupts = <48 0x8>;
27 interrupt-parent = <&ipic>;
30 FPGA1:iocon_uart@2,0 {
31 reg = <0x2 0x0 0x100000>;
33 interrupts = <17 0x8>;
34 interrupt-parent = <&ipic>;
39 compatible = "gdsys,iocon_fpga";
46 audio_base = <0x0040>;
47 timebase_base = <0x013c>;
50 * for every interrupt source there must be a dataset specifying
51 * 1. type (1: standard)
52 * 2. status register offset
53 * 3. mask register offset
56 fpga_interrupt_sources =
57 <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
58 <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
60 * for every interrupt there must be a dataset specifying
61 * 1. type (1: status, 2: event)
62 * 2. interrupt source index
63 * 3. interrupt register bit
64 * 4. mask register bit
66 #fpga_interrupt_map-cells = <4>;
68 <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
69 <1 0 0 0>, /* 1: VIDEO 0 */
70 <1 0 1 1>, /* 2: VIDEO 1 */
71 <1 0 2 2>, /* 3: VIDEO IC 0 */
72 <1 0 3 3>, /* 4: VIDEO IC 1 */
73 <1 0 4 4>, /* 5: IIC MAIN */
74 <1 0 6 6>, /* 6: IIC VIDEO 0 */
75 <1 0 7 7>, /* 7: IIC VIDEO 1 */
76 <1 1 0 0>, /* 8: OSD 0 */
77 <1 1 1 1>, /* 9: OSD 1 */
78 <1 1 2 2>, /* 10: SPDIF 0 */
79 <1 1 3 3>, /* 11: SPDIF 1 */
80 <1 0 12 12>, /* 12: COMM 0 */
81 <1 0 13 13>, /* 13: COMM 1 */
82 <1 0 10 10>, /* 14: COMM 2 */
83 <1 0 11 11>, /* 15: COMM 3 */
84 <2 0 5 5>, /* 16: MDIO */
85 <1 0 8 8>, /* 17: PHY */
86 <1 1 4 4>, /* 18: RS232 */
87 <1 1 5 5>, /* 19: AUDIO */
88 <1 1 8 8>, /* 20: PROC_AUDIO */
89 <1 1 7 7>, /* 21: USB/ETH-UART INT */
90 <2 1 10 10>, /* 22: AXI Bridge 0 */
91 <2 1 11 11>, /* 23: AXI Bridge 1 */
92 <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
97 compatible = "gdsys,iocon_fpga";
104 audio_base = <0x0040>;
105 timebase_base = <0x013c>;
108 * for every interrupt source there must be a dataset specifying
109 * 1. type (1: standard)
110 * 2. status register offset
111 * 3. mask register offset
114 fpga_interrupt_sources =
115 <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
116 <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
118 * for every interrupt there must be a dataset specifying
119 * 1. type (1: status, 2: event)
120 * 2. interrupt source index
121 * 3. interrupt register bit
122 * 4. mask register bit
124 #fpga_interrupt_map-cells = <4>;
126 <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
127 <1 0 0 0>, /* 1: VIDEO 0 */
128 <1 0 1 1>, /* 2: VIDEO 1 */
129 <1 0 2 2>, /* 3: VIDEO IC 0 */
130 <1 0 3 3>, /* 4: VIDEO IC 1 */
131 <1 0 4 4>, /* 5: IIC MAIN */
132 <1 0 6 6>, /* 6: IIC VIDEO 0 */
133 <1 0 7 7>, /* 7: IIC VIDEO 1 */
134 <1 1 0 0>, /* 8: OSD 0 */
135 <1 1 1 1>, /* 9: OSD 1 */
136 <1 1 2 2>, /* 10: SPDIF 0 */
137 <1 1 3 3>, /* 11: SPDIF 1 */
138 <1 0 12 12>, /* 12: COMM 0 */
139 <1 0 13 13>, /* 13: COMM 1 */
140 <1 0 10 10>, /* 14: COMM 2 */
141 <1 0 11 11>, /* 15: COMM 3 */
142 <2 0 5 5>, /* 16: MDIO */
143 <1 0 8 8>, /* 17: PHY */
144 <1 1 4 4>, /* 18: RS232 */
145 <1 1 5 5>, /* 19: AUDIO */
146 <1 1 8 8>, /* 20: PROC_AUDIO */
147 <1 1 7 7>, /* 21: USB/ETH-UART INT */
148 <2 1 10 10>, /* 22: AXI Bridge 0 */
149 <2 1 11 11>, /* 23: AXI Bridge 1 */
150 <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
156 #address-cells = <1>;
158 ranges = <0 0 0x00002000>;
160 compatible = "gdsys,soc";
163 compatible = "gdsys,ihs_trans_rs232";
169 compatible = "gdsys,ihs_simple_uart";
172 fpga_interrupts = <21>;
177 compatible = "gdsys,ihs_i2cmaster";
180 fpga_interrupts = <5>;
181 #address-cells = <1>;
184 fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
185 compatible = "ti,sn75dp130";
187 eq-i2c-enable = <3 2 1 0
190 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
192 fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
193 compatible = "ti,sn75dp130";
195 eq-i2c-enable = <3 2 1 0
198 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
201 compatible = "national,lm77";
205 compatible = "ti,ads1015";
209 compatible = "ti,ads1015";
215 compatible = "gdsys,ihs_video_out";
218 fpga_interrupts = <1 8>; /* VIDEO OSD */
220 osd_buffer_base = <0x1000>;
221 spdif_audio_base = <0x1e0>;
226 fpga-pb-pixels = <2730>; /* 8192 / 3 */
228 video_tx = <&fpga0_dp_video0>;
229 clk_gen = <&fpga0_video0_clkgen>;
230 ddc_ci = <&fpga0_dp_video0>;
234 compatible = "gdsys,ihs_i2cmaster";
237 fpga_interrupts = <6>;
238 #address-cells = <1>;
241 fpga0_video0_clkgen: fpga0_video0_clkgen {
242 compatible = "idt,ics8n3qv01";
249 #address-cells = <1>;
251 compatible = "gdsys,ihs_axi";
254 fpga_interrupts = <22>;
256 fpga0_dp_video0: fpga0_dp_video0 {
257 compatible = "gdsys,logicore_dp_tx";
258 reg = <0x44a10000 0x1000>;
260 redriver = <&fpga0_dp_video0_redriver>;
266 compatible = "gdsys,ihs_video_out";
269 fpga_interrupts = <2 9>; /* VIDEO OSD */
271 osd_buffer_base = <0x2000>;
272 spdif_audio_base = <0x2e0>;
277 fpga-pb-pixels = <2730>; /* 8192 / 3 */
279 video_tx = <&fpga0_dp_video1>;
280 clk_gen = <&fpga0_video1_clkgen>;
281 ddc_ci = <&fpga0_dp_video1>;
285 compatible = "gdsys,ihs_i2cmaster";
288 fpga_interrupts = <7>;
289 #address-cells = <1>;
292 fpga0_video1_clkgen: fpga0_video1_clkgen {
293 compatible = "idt,ics8n3qv01";
300 #address-cells = <1>;
302 compatible = "gdsys,ihs_axi";
305 fpga_interrupts = <23>;
307 fpga0_dp_video1: fpga0_dp_video1 {
308 compatible = "gdsys,logicore_dp_tx";
309 reg = <0x44a10000 0x1000>;
311 redriver = <&fpga0_dp_video1_redriver>;
317 compatible = "gdsys,ihs_i2cmaster";
320 fpga_interrupts = <24>;
321 #address-cells = <1>;
325 compatible = "nxp,pca9555";
333 compatible = "gdsys,io-endpoint";
340 fpga_interrupts = <12 13 14 15>;
342 nprot_channel = <16>;
349 compatible = "gdsys,ihs_mdiomaster";
352 fpga_interrupts = <16>;
353 #address-cells = <1>;
357 compatible = "ethernet-phy-ieee802.3-c45";
358 device_type ="ethernet-phy";
362 compatible = "ethernet-phy-ieee802.3-c45";
363 device_type ="ethernet-phy";
367 compatible = "ethernet-phy-ieee802.3-c45";
368 device_type ="ethernet-phy";
372 compatible = "ethernet-phy-ieee802.3-c45";
373 device_type ="ethernet-phy";
382 #address-cells = <1>;
384 ranges = <0 0 0x00002000>;
386 compatible = "gdsys,soc";
389 compatible = "gdsys,ihs_simple_uart";
392 fpga_interrupts = <21>;
393 line = <4>; /* TODO check and FIX */
397 compatible = "gdsys,ihs_i2cmaster";
400 fpga_interrupts = <5>;
401 #address-cells = <1>;
404 fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
405 compatible = "ti,sn75dp130";
407 eq-i2c-enable = <3 2 1 0
410 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
412 fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
413 compatible = "ti,sn75dp130";
415 eq-i2c-enable = <3 2 1 0
418 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
421 compatible = "national,lm77";
425 compatible = "ti,ads1015";
429 compatible = "ti,ads1015";
435 compatible = "gdsys,ihs_video_out";
438 fpga_interrupts = <1 8>; /* VIDEO OSD */
440 osd_buffer_base = <0x1000>;
441 spdif_audio_base = <0x1e0>;
446 fpga-pb-pixels = <2730>; /* 8192 / 3 */
448 video_tx = <&fpga1_dp_video0>;
449 clk_gen = <&fpga1_video0_clkgen>;
450 ddc_ci = <&fpga1_dp_video0>;
454 compatible = "gdsys,ihs_i2cmaster";
457 fpga_interrupts = <6>;
458 #address-cells = <1>;
461 fpga1_video0_clkgen: fpga1_video0_clkgen {
462 compatible = "idt,ics8n3qv01";
469 #address-cells = <1>;
471 compatible = "gdsys,ihs_axi";
474 fpga_interrupts = <22>;
476 fpga1_dp_video0: fpga1_dp_video0 {
477 compatible = "gdsys,logicore_dp_tx";
478 reg = <0x44a10000 0x1000>;
480 redriver = <&fpga1_dp_video0_redriver>;
486 compatible = "gdsys,ihs_video_out";
489 fpga_interrupts = <2 9>; /* VIDEO OSD */
491 osd_buffer_base = <0x2000>;
492 spdif_audio_base = <0x2e0>;
497 fpga-pb-pixels = <2730>; /* 8192 / 3 */
499 video_tx = <&fpga1_dp_video1>;
500 clk_gen = <&fpga1_video1_clkgen>;
501 ddc_ci = <&fpga1_dp_video1>;
505 compatible = "gdsys,ihs_i2cmaster";
508 fpga_interrupts = <7>;
509 #address-cells = <1>;
512 fpga1_video1_clkgen: fpga1_video1_clkgen {
513 compatible = "idt,ics8n3qv01";
520 #address-cells = <1>;
522 compatible = "gdsys,ihs_axi";
525 fpga_interrupts = <23>;
527 fpga1_dp_video1: fpga1_dp_video1 {
528 compatible = "gdsys,logicore_dp_tx";
529 reg = <0x44a10000 0x1000>;
531 redriver = <&fpga1_dp_video1_redriver>;
537 compatible = "gdsys,ihs_i2cmaster";
540 fpga_interrupts = <24>;
541 #address-cells = <1>;
545 compatible = "nxp,pca9555";
553 compatible = "gdsys,io-endpoint";
560 fpga_interrupts = <12 13 14 15>;
562 nprot_channel = <17>;
569 compatible = "gdsys,ihs_mdiomaster";
572 fpga_interrupts = <16>;
573 #address-cells = <1>;
577 compatible = "ethernet-phy-ieee802.3-c45";
578 device_type ="ethernet-phy";
582 compatible = "ethernet-phy-ieee802.3-c45";
583 device_type ="ethernet-phy";
587 compatible = "ethernet-phy-ieee802.3-c45";
588 device_type ="ethernet-phy";
592 compatible = "ethernet-phy-ieee802.3-c45";
593 device_type ="ethernet-phy";
602 #include "gdsys/gazerbeam-uboot.dtsi"