board_f: Drop return value from initdram()
[oweals/u-boot.git] / arch / powerpc / cpu / ppc4xx / denali_spd_ddr2.c
1 /*
2  * arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
3  * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
4  * DDR2 controller, specifically the 440EPx/GRx.
5  *
6  * (C) Copyright 2007-2008
7  * Larry Johnson, lrj@acm.org.
8  *
9  * Based primarily on arch/powerpc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
10  *
11  * (C) Copyright 2007
12  * Stefan Roese, DENX Software Engineering, sr@denx.de.
13  *
14  * COPYRIGHT   AMCC   CORPORATION 2004
15  *
16  * SPDX-License-Identifier:     GPL-2.0+
17  */
18
19 /* define DEBUG for debugging output (obviously ;-)) */
20 #if 0
21 #define DEBUG
22 #endif
23
24 #include <common.h>
25 #include <command.h>
26 #include <asm/ppc4xx.h>
27 #include <i2c.h>
28 #include <asm/io.h>
29 #include <asm/processor.h>
30 #include <asm/mmu.h>
31 #include <asm/cache.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #if defined(CONFIG_SPD_EEPROM) &&                               \
36         (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
37
38 /*-----------------------------------------------------------------------------+
39  * Defines
40  *-----------------------------------------------------------------------------*/
41 #define MAXDIMMS        2
42 #define MAXRANKS        2
43
44 #define ONE_BILLION     1000000000
45
46 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
47
48 #define DLL_DQS_DELAY   0x19
49 #define DLL_DQS_BYPASS  0x0B
50 #define DQS_OUT_SHIFT   0x7F
51
52 /*
53  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
54  * region. Right now the cache should still be disabled in U-Boot because of the
55  * EMAC driver, that need it's buffer descriptor to be located in non cached
56  * memory.
57  *
58  * If at some time this restriction doesn't apply anymore, just define
59  * CONFIG_4xx_DCACHE in the board config file and this code should setup
60  * everything correctly.
61  */
62 #if defined(CONFIG_4xx_DCACHE)
63 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
64 #else
65 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
66 #endif
67
68 /*-----------------------------------------------------------------------------+
69  * Prototypes
70  *-----------------------------------------------------------------------------*/
71 extern int denali_wait_for_dlllock(void);
72 extern void denali_core_search_data_eye(void);
73 extern void dcbz_area(u32 start_address, u32 num_bytes);
74
75 /*
76  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
77  */
78 void __spd_ddr_init_hang(void)
79 {
80         hang();
81 }
82 void spd_ddr_init_hang(void)
83     __attribute__ ((weak, alias("__spd_ddr_init_hang")));
84
85 #if defined(DEBUG)
86 static void print_mcsr(void)
87 {
88         printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
89 }
90
91 static void denali_sdram_register_dump(void)
92 {
93         unsigned int sdram_data;
94
95         printf("\n  Register Dump:\n");
96         mfsdram(DDR0_00, sdram_data);
97         printf("        DDR0_00 = 0x%08X", sdram_data);
98         mfsdram(DDR0_01, sdram_data);
99         printf("        DDR0_01 = 0x%08X\n", sdram_data);
100         mfsdram(DDR0_02, sdram_data);
101         printf("        DDR0_02 = 0x%08X", sdram_data);
102         mfsdram(DDR0_03, sdram_data);
103         printf("        DDR0_03 = 0x%08X\n", sdram_data);
104         mfsdram(DDR0_04, sdram_data);
105         printf("        DDR0_04 = 0x%08X", sdram_data);
106         mfsdram(DDR0_05, sdram_data);
107         printf("        DDR0_05 = 0x%08X\n", sdram_data);
108         mfsdram(DDR0_06, sdram_data);
109         printf("        DDR0_06 = 0x%08X", sdram_data);
110         mfsdram(DDR0_07, sdram_data);
111         printf("        DDR0_07 = 0x%08X\n", sdram_data);
112         mfsdram(DDR0_08, sdram_data);
113         printf("        DDR0_08 = 0x%08X", sdram_data);
114         mfsdram(DDR0_09, sdram_data);
115         printf("        DDR0_09 = 0x%08X\n", sdram_data);
116         mfsdram(DDR0_10, sdram_data);
117         printf("        DDR0_10 = 0x%08X", sdram_data);
118         mfsdram(DDR0_11, sdram_data);
119         printf("        DDR0_11 = 0x%08X\n", sdram_data);
120         mfsdram(DDR0_12, sdram_data);
121         printf("        DDR0_12 = 0x%08X", sdram_data);
122         mfsdram(DDR0_14, sdram_data);
123         printf("        DDR0_14 = 0x%08X\n", sdram_data);
124         mfsdram(DDR0_17, sdram_data);
125         printf("        DDR0_17 = 0x%08X", sdram_data);
126         mfsdram(DDR0_18, sdram_data);
127         printf("        DDR0_18 = 0x%08X\n", sdram_data);
128         mfsdram(DDR0_19, sdram_data);
129         printf("        DDR0_19 = 0x%08X", sdram_data);
130         mfsdram(DDR0_20, sdram_data);
131         printf("        DDR0_20 = 0x%08X\n", sdram_data);
132         mfsdram(DDR0_21, sdram_data);
133         printf("        DDR0_21 = 0x%08X", sdram_data);
134         mfsdram(DDR0_22, sdram_data);
135         printf("        DDR0_22 = 0x%08X\n", sdram_data);
136         mfsdram(DDR0_23, sdram_data);
137         printf("        DDR0_23 = 0x%08X", sdram_data);
138         mfsdram(DDR0_24, sdram_data);
139         printf("        DDR0_24 = 0x%08X\n", sdram_data);
140         mfsdram(DDR0_25, sdram_data);
141         printf("        DDR0_25 = 0x%08X", sdram_data);
142         mfsdram(DDR0_26, sdram_data);
143         printf("        DDR0_26 = 0x%08X\n", sdram_data);
144         mfsdram(DDR0_27, sdram_data);
145         printf("        DDR0_27 = 0x%08X", sdram_data);
146         mfsdram(DDR0_28, sdram_data);
147         printf("        DDR0_28 = 0x%08X\n", sdram_data);
148         mfsdram(DDR0_31, sdram_data);
149         printf("        DDR0_31 = 0x%08X", sdram_data);
150         mfsdram(DDR0_32, sdram_data);
151         printf("        DDR0_32 = 0x%08X\n", sdram_data);
152         mfsdram(DDR0_33, sdram_data);
153         printf("        DDR0_33 = 0x%08X", sdram_data);
154         mfsdram(DDR0_34, sdram_data);
155         printf("        DDR0_34 = 0x%08X\n", sdram_data);
156         mfsdram(DDR0_35, sdram_data);
157         printf("        DDR0_35 = 0x%08X", sdram_data);
158         mfsdram(DDR0_36, sdram_data);
159         printf("        DDR0_36 = 0x%08X\n", sdram_data);
160         mfsdram(DDR0_37, sdram_data);
161         printf("        DDR0_37 = 0x%08X", sdram_data);
162         mfsdram(DDR0_38, sdram_data);
163         printf("        DDR0_38 = 0x%08X\n", sdram_data);
164         mfsdram(DDR0_39, sdram_data);
165         printf("        DDR0_39 = 0x%08X", sdram_data);
166         mfsdram(DDR0_40, sdram_data);
167         printf("        DDR0_40 = 0x%08X\n", sdram_data);
168         mfsdram(DDR0_41, sdram_data);
169         printf("        DDR0_41 = 0x%08X", sdram_data);
170         mfsdram(DDR0_42, sdram_data);
171         printf("        DDR0_42 = 0x%08X\n", sdram_data);
172         mfsdram(DDR0_43, sdram_data);
173         printf("        DDR0_43 = 0x%08X", sdram_data);
174         mfsdram(DDR0_44, sdram_data);
175         printf("        DDR0_44 = 0x%08X\n", sdram_data);
176 }
177 #else
178 static inline void denali_sdram_register_dump(void)
179 {
180 }
181
182 inline static void print_mcsr(void)
183 {
184 }
185 #endif /* defined(DEBUG) */
186
187 static int is_ecc_enabled(void)
188 {
189         u32 val;
190
191         mfsdram(DDR0_22, val);
192         return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
193 }
194
195 static unsigned char spd_read(u8 chip, unsigned int addr)
196 {
197         u8 data[2];
198
199         if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
200                 debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
201                 return 0;
202         }
203         debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
204               chip, addr, data[0]);
205         return data[0];
206 }
207
208 static unsigned long get_tcyc(unsigned char reg)
209 {
210         /*
211          * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
212          * nibbles: the higher order nibble (bits 4-7) designates the cycle time
213          * to a granularity of 1ns; the value presented by the lower order
214          * nibble (bits 0-3) has a granularity of .1ns and is added to the value
215          * designated by the higher nibble. In addition, four lines of the lower
216          * order nibble are assigned to support +.25, +.33, +.66, and +.75.
217          */
218
219         unsigned char subfield_b = reg & 0x0F;
220
221         switch (subfield_b & 0x0F) {
222         case 0x0:
223         case 0x1:
224         case 0x2:
225         case 0x3:
226         case 0x4:
227         case 0x5:
228         case 0x6:
229         case 0x7:
230         case 0x8:
231         case 0x9:
232                 return 1000 * (reg >> 4) + 100 * subfield_b;
233         case 0xA:
234                 return 1000 * (reg >> 4) + 250;
235         case 0xB:
236                 return 1000 * (reg >> 4) + 333;
237         case 0xC:
238                 return 1000 * (reg >> 4) + 667;
239         case 0xD:
240                 return 1000 * (reg >> 4) + 750;
241         }
242         return 0;
243 }
244
245 /*------------------------------------------------------------------
246  * Find the installed DIMMs, make sure that the are DDR2, and fill
247  * in the dimm_ranks array.  Then dimm_ranks[dimm_num] > 0 iff the
248  * DIMM and dimm_num is present.
249  * Note: Because there are only two chip-select lines, it is assumed
250  * that a board with a single socket can support two ranks on that
251  * socket, while a board with two sockets can support only one rank
252  * on each socket.
253  *-----------------------------------------------------------------*/
254 static void get_spd_info(unsigned long dimm_ranks[],
255                          unsigned long *ranks,
256                          unsigned char const iic0_dimm_addr[],
257                          unsigned long num_dimm_banks)
258 {
259         unsigned long dimm_num;
260         unsigned long dimm_found = false;
261         unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
262         unsigned char num_of_bytes;
263         unsigned char total_size;
264
265         *ranks = 0;
266         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
267                 num_of_bytes = 0;
268                 total_size = 0;
269
270                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
271                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
272                 if ((num_of_bytes != 0) && (total_size != 0)) {
273                         unsigned char const dimm_type =
274                             spd_read(iic0_dimm_addr[dimm_num], 2);
275
276                         unsigned long ranks_on_dimm =
277                             (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
278
279                         if (8 != dimm_type) {
280                                 switch (dimm_type) {
281                                 case 1:
282                                         printf("ERROR: Standard Fast Page Mode "
283                                                "DRAM DIMM");
284                                         break;
285                                 case 2:
286                                         printf("ERROR: EDO DIMM");
287                                         break;
288                                 case 3:
289                                         printf("ERROR: Pipelined Nibble DIMM");
290                                         break;
291                                 case 4:
292                                         printf("ERROR: SDRAM DIMM");
293                                         break;
294                                 case 5:
295                                         printf("ERROR: Multiplexed ROM DIMM");
296                                         break;
297                                 case 6:
298                                         printf("ERROR: SGRAM DIMM");
299                                         break;
300                                 case 7:
301                                         printf("ERROR: DDR1 DIMM");
302                                         break;
303                                 default:
304                                         printf("ERROR: Unknown DIMM (type %d)",
305                                                (unsigned int)dimm_type);
306                                         break;
307                                 }
308                                 printf(" detected in slot %lu.\n", dimm_num);
309                                 printf("Only DDR2 SDRAM DIMMs are supported."
310                                        "\n");
311                                 printf("Replace the module with a DDR2 DIMM."
312                                        "\n\n");
313                                 spd_ddr_init_hang();
314                         }
315                         dimm_found = true;
316                         debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
317                               "\n", dimm_num, ranks_on_dimm);
318                         if (ranks_on_dimm > max_ranks_per_dimm) {
319                                 printf("WARNING: DRAM DIMM in slot %lu has %lu "
320                                        "ranks.\n", dimm_num, ranks_on_dimm);
321                                 if (1 == max_ranks_per_dimm) {
322                                         printf("Only one rank will be used.\n");
323                                 } else {
324                                         printf
325                                             ("Only two ranks will be used.\n");
326                                 }
327                                 ranks_on_dimm = max_ranks_per_dimm;
328                         }
329                         dimm_ranks[dimm_num] = ranks_on_dimm;
330                         *ranks += ranks_on_dimm;
331                 } else {
332                         dimm_ranks[dimm_num] = 0;
333                         debug("DIMM slot %lu: Not populated\n", dimm_num);
334                 }
335         }
336         if (dimm_found == false) {
337                 printf("ERROR: No memory installed.\n");
338                 printf("Install at least one DDR2 DIMM.\n\n");
339                 spd_ddr_init_hang();
340         }
341         debug("Total number of ranks = %ld\n", *ranks);
342 }
343
344 /*------------------------------------------------------------------
345  * For the memory DIMMs installed, this routine verifies that
346  * frequency previously calculated is supported.
347  *-----------------------------------------------------------------*/
348 static void check_frequency(unsigned long *dimm_ranks,
349                             unsigned char const iic0_dimm_addr[],
350                             unsigned long num_dimm_banks,
351                             unsigned long sdram_freq)
352 {
353         unsigned long dimm_num;
354         unsigned long cycle_time;
355         unsigned long calc_cycle_time;
356
357         /*
358          * calc_cycle_time is calculated from DDR frequency set by board/chip
359          * and is expressed in picoseconds to match the way DIMM cycle time is
360          * calculated below.
361          */
362         calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
363
364         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
365                 if (dimm_ranks[dimm_num]) {
366                         cycle_time =
367                             get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
368                         debug("cycle_time=%ld ps\n", cycle_time);
369
370                         if (cycle_time > (calc_cycle_time + 10)) {
371                                 /*
372                                  * the provided sdram cycle_time is too small
373                                  * for the available DIMM cycle_time. The
374                                  * additionnal 10ps is here to accept a small
375                                  * incertainty.
376                                  */
377                                 printf
378                                     ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
379                                      "slot %d \n while calculated cycle time is %d ps.\n",
380                                      (unsigned int)cycle_time,
381                                      (unsigned int)dimm_num,
382                                      (unsigned int)calc_cycle_time);
383                                 printf
384                                     ("Replace the DIMM, or change DDR frequency via "
385                                      "strapping bits.\n\n");
386                                 spd_ddr_init_hang();
387                         }
388                 }
389         }
390 }
391
392 /*------------------------------------------------------------------
393  * This routine gets size information for the installed memory
394  * DIMMs.
395  *-----------------------------------------------------------------*/
396 static void get_dimm_size(unsigned long dimm_ranks[],
397                           unsigned char const iic0_dimm_addr[],
398                           unsigned long num_dimm_banks,
399                           unsigned long *const rows,
400                           unsigned long *const banks,
401                           unsigned long *const cols, unsigned long *const width)
402 {
403         unsigned long dimm_num;
404
405         *rows = 0;
406         *banks = 0;
407         *cols = 0;
408         *width = 0;
409         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
410                 if (dimm_ranks[dimm_num]) {
411                         unsigned long t;
412
413                         /* Rows */
414                         t = spd_read(iic0_dimm_addr[dimm_num], 3);
415                         if (0 == *rows) {
416                                 *rows = t;
417                         } else if (t != *rows) {
418                                 printf("ERROR: DRAM DIMM modules do not all "
419                                        "have the same number of rows.\n\n");
420                                 spd_ddr_init_hang();
421                         }
422                         /* Banks */
423                         t = spd_read(iic0_dimm_addr[dimm_num], 17);
424                         if (0 == *banks) {
425                                 *banks = t;
426                         } else if (t != *banks) {
427                                 printf("ERROR: DRAM DIMM modules do not all "
428                                        "have the same number of banks.\n\n");
429                                 spd_ddr_init_hang();
430                         }
431                         /* Columns */
432                         t = spd_read(iic0_dimm_addr[dimm_num], 4);
433                         if (0 == *cols) {
434                                 *cols = t;
435                         } else if (t != *cols) {
436                                 printf("ERROR: DRAM DIMM modules do not all "
437                                        "have the same number of columns.\n\n");
438                                 spd_ddr_init_hang();
439                         }
440                         /* Data width */
441                         t = spd_read(iic0_dimm_addr[dimm_num], 6);
442                         if (0 == *width) {
443                                 *width = t;
444                         } else if (t != *width) {
445                                 printf("ERROR: DRAM DIMM modules do not all "
446                                        "have the same data width.\n\n");
447                                 spd_ddr_init_hang();
448                         }
449                 }
450         }
451         debug("Number of rows = %ld\n", *rows);
452         debug("Number of columns = %ld\n", *cols);
453         debug("Number of banks = %ld\n", *banks);
454         debug("Data width = %ld\n", *width);
455         if (*rows > 14) {
456                 printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
457                        *rows);
458                 printf("Only modules with 14 or fewer rows are supported.\n\n");
459                 spd_ddr_init_hang();
460         }
461         if (4 != *banks && 8 != *banks) {
462                 printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
463                 printf("Only modules with 4 or 8 banks are supported.\n\n");
464                 spd_ddr_init_hang();
465         }
466         if (*cols > 12) {
467                 printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
468                        *cols);
469                 printf("Only modules with 12 or fewer columns are "
470                        "supported.\n\n");
471                 spd_ddr_init_hang();
472         }
473         if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
474                 printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
475                        *width);
476                 printf("Only modules with widths of 32, 40, 64, and 72 bits "
477                        "are supported.\n\n");
478                 spd_ddr_init_hang();
479         }
480 }
481
482 /*------------------------------------------------------------------
483  * Only 1.8V modules are supported.  This routine verifies this.
484  *-----------------------------------------------------------------*/
485 static void check_voltage_type(unsigned long dimm_ranks[],
486                                unsigned char const iic0_dimm_addr[],
487                                unsigned long num_dimm_banks)
488 {
489         unsigned long dimm_num;
490         unsigned long voltage_type;
491
492         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
493                 if (dimm_ranks[dimm_num]) {
494                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
495                         if (0x05 != voltage_type) {     /* 1.8V for DDR2 */
496                                 printf("ERROR: Slot %lu provides 1.8V for DDR2 "
497                                        "DIMMs.\n", dimm_num);
498                                 switch (voltage_type) {
499                                 case 0x00:
500                                         printf("This DIMM is 5.0 Volt/TTL.\n");
501                                         break;
502                                 case 0x01:
503                                         printf("This DIMM is LVTTL.\n");
504                                         break;
505                                 case 0x02:
506                                         printf("This DIMM is 1.5 Volt.\n");
507                                         break;
508                                 case 0x03:
509                                         printf("This DIMM is 3.3 Volt/TTL.\n");
510                                         break;
511                                 case 0x04:
512                                         printf("This DIMM is 2.5 Volt.\n");
513                                         break;
514                                 default:
515                                         printf("This DIMM is an unknown "
516                                                "voltage.\n");
517                                         break;
518                                 }
519                                 printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
520                                 spd_ddr_init_hang();
521                         }
522                 }
523         }
524 }
525
526 static void program_ddr0_03(unsigned long dimm_ranks[],
527                             unsigned char const iic0_dimm_addr[],
528                             unsigned long num_dimm_banks,
529                             unsigned long sdram_freq,
530                             unsigned long rows, unsigned long *cas_latency)
531 {
532         unsigned long dimm_num;
533         unsigned long cas_index;
534         unsigned long cycle_2_0_clk;
535         unsigned long cycle_3_0_clk;
536         unsigned long cycle_4_0_clk;
537         unsigned long cycle_5_0_clk;
538         unsigned long max_2_0_tcyc_ps = 100;
539         unsigned long max_3_0_tcyc_ps = 100;
540         unsigned long max_4_0_tcyc_ps = 100;
541         unsigned long max_5_0_tcyc_ps = 100;
542         unsigned char cas_available = 0x3C;     /* value for DDR2 */
543         u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
544         unsigned int const tcyc_addr[3] = { 9, 23, 25 };
545
546         /*------------------------------------------------------------------
547          * Get the board configuration info.
548          *-----------------------------------------------------------------*/
549         debug("sdram_freq = %ld\n", sdram_freq);
550
551         /*------------------------------------------------------------------
552          * Handle the timing.  We need to find the worst case timing of all
553          * the dimm modules installed.
554          *-----------------------------------------------------------------*/
555         /* loop through all the DIMM slots on the board */
556         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
557                 /* If a dimm is installed in a particular slot ... */
558                 if (dimm_ranks[dimm_num]) {
559                         unsigned char const cas_bit =
560                             spd_read(iic0_dimm_addr[dimm_num], 18);
561                         unsigned char cas_mask;
562
563                         cas_available &= cas_bit;
564                         for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
565                                 if (cas_bit & cas_mask)
566                                         break;
567                         }
568                         debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
569                               cas_bit, cas_mask);
570
571                         for (cas_index = 0; cas_index < 3;
572                              cas_mask >>= 1, cas_index++) {
573                                 unsigned long cycle_time_ps;
574
575                                 if (!(cas_available & cas_mask)) {
576                                         continue;
577                                 }
578                                 cycle_time_ps =
579                                     get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
580                                                       tcyc_addr[cas_index]));
581
582                                 debug("cas_index = %ld: cycle_time_ps = %ld\n",
583                                       cas_index, cycle_time_ps);
584                                 /*
585                                  * DDR2 devices use the following bitmask for CAS latency:
586                                  *  Bit   7    6    5    4    3    2    1    0
587                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
588                                  */
589                                 switch (cas_mask) {
590                                 case 0x20:
591                                         max_5_0_tcyc_ps =
592                                             max(max_5_0_tcyc_ps, cycle_time_ps);
593                                         break;
594                                 case 0x10:
595                                         max_4_0_tcyc_ps =
596                                             max(max_4_0_tcyc_ps, cycle_time_ps);
597                                         break;
598                                 case 0x08:
599                                         max_3_0_tcyc_ps =
600                                             max(max_3_0_tcyc_ps, cycle_time_ps);
601                                         break;
602                                 case 0x04:
603                                         max_2_0_tcyc_ps =
604                                             max(max_2_0_tcyc_ps, cycle_time_ps);
605                                         break;
606                                 }
607                         }
608                 }
609         }
610         debug("cas_available (bit map) = 0x%02X\n", cas_available);
611
612         /*------------------------------------------------------------------
613          * Set the SDRAM mode, SDRAM_MMODE
614          *-----------------------------------------------------------------*/
615
616         /* add 10 here because of rounding problems */
617         cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
618         cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
619         cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
620         cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
621         debug("cycle_2_0_clk = %ld\n", cycle_2_0_clk);
622         debug("cycle_3_0_clk = %ld\n", cycle_3_0_clk);
623         debug("cycle_4_0_clk = %ld\n", cycle_4_0_clk);
624         debug("cycle_5_0_clk = %ld\n", cycle_5_0_clk);
625
626         if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
627                 *cas_latency = 2;
628                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
629                     DDR0_03_CASLAT_LIN_ENCODE(0x4);
630         } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
631                 *cas_latency = 3;
632                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
633                     DDR0_03_CASLAT_LIN_ENCODE(0x6);
634         } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
635                 *cas_latency = 4;
636                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
637                     DDR0_03_CASLAT_LIN_ENCODE(0x8);
638         } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
639                 *cas_latency = 5;
640                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
641                     DDR0_03_CASLAT_LIN_ENCODE(0xA);
642         } else {
643                 printf("ERROR: Cannot find a supported CAS latency with the "
644                        "installed DIMMs.\n");
645                 printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
646                        "and 5.0 are supported.\n");
647                 printf("Make sure the PLB speed is within the supported range "
648                        "of the DIMMs.\n");
649                 printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
650                        "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
651                        cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
652                 spd_ddr_init_hang();
653         }
654         debug("CAS latency = %ld\n", *cas_latency);
655         mtsdram(DDR0_03, ddr0_03);
656 }
657
658 static void program_ddr0_04(unsigned long dimm_ranks[],
659                             unsigned char const iic0_dimm_addr[],
660                             unsigned long num_dimm_banks,
661                             unsigned long sdram_freq)
662 {
663         unsigned long dimm_num;
664         unsigned long t_rc_ps = 0;
665         unsigned long t_rrd_ps = 0;
666         unsigned long t_rtp_ps = 0;
667         unsigned long t_rc_clk;
668         unsigned long t_rrd_clk;
669         unsigned long t_rtp_clk;
670
671         /*------------------------------------------------------------------
672          * Handle the timing.  We need to find the worst case timing of all
673          * the dimm modules installed.
674          *-----------------------------------------------------------------*/
675         /* loop through all the DIMM slots on the board */
676         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
677                 /* If a dimm is installed in a particular slot ... */
678                 if (dimm_ranks[dimm_num]) {
679                         unsigned long ps;
680
681                         /* tRC */
682                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
683                         switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
684                         case 0x1:
685                                 ps += 250;
686                                 break;
687                         case 0x2:
688                                 ps += 333;
689                                 break;
690                         case 0x3:
691                                 ps += 500;
692                                 break;
693                         case 0x4:
694                                 ps += 667;
695                                 break;
696                         case 0x5:
697                                 ps += 750;
698                                 break;
699                         }
700                         t_rc_ps = max(t_rc_ps, ps);
701                         /* tRRD */
702                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
703                         t_rrd_ps = max(t_rrd_ps, ps);
704                         /* tRTP */
705                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
706                         t_rtp_ps = max(t_rtp_ps, ps);
707                 }
708         }
709         debug("t_rc_ps  = %ld\n", t_rc_ps);
710         t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
711         debug("t_rrd_ps = %ld\n", t_rrd_ps);
712         t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
713         debug("t_rtp_ps = %ld\n", t_rtp_ps);
714         t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
715         mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
716                 DDR0_04_TRRD_ENCODE(t_rrd_clk) |
717                 DDR0_04_TRTP_ENCODE(t_rtp_clk));
718 }
719
720 static void program_ddr0_05(unsigned long dimm_ranks[],
721                             unsigned char const iic0_dimm_addr[],
722                             unsigned long num_dimm_banks,
723                             unsigned long sdram_freq)
724 {
725         unsigned long dimm_num;
726         unsigned long t_rp_ps = 0;
727         unsigned long t_ras_ps = 0;
728         unsigned long t_rp_clk;
729         unsigned long t_ras_clk;
730         u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
731
732         /*------------------------------------------------------------------
733          * Handle the timing.  We need to find the worst case timing of all
734          * the dimm modules installed.
735          *-----------------------------------------------------------------*/
736         /* loop through all the DIMM slots on the board */
737         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
738                 /* If a dimm is installed in a particular slot ... */
739                 if (dimm_ranks[dimm_num]) {
740                         unsigned long ps;
741
742                         /* tRP */
743                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
744                         t_rp_ps = max(t_rp_ps, ps);
745                         /* tRAS */
746                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
747                         t_ras_ps = max(t_ras_ps, ps);
748                 }
749         }
750         debug("t_rp_ps  = %ld\n", t_rp_ps);
751         t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
752         debug("t_ras_ps = %ld\n", t_ras_ps);
753         t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
754         mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
755                 DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
756 }
757
758 static void program_ddr0_06(unsigned long dimm_ranks[],
759                             unsigned char const iic0_dimm_addr[],
760                             unsigned long num_dimm_banks,
761                             unsigned long sdram_freq)
762 {
763         unsigned long dimm_num;
764         unsigned char spd_40;
765         unsigned long t_wtr_ps = 0;
766         unsigned long t_rfc_ps = 0;
767         unsigned long t_wtr_clk;
768         unsigned long t_rfc_clk;
769         u32 ddr0_06 =
770             DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
771
772         /*------------------------------------------------------------------
773          * Handle the timing.  We need to find the worst case timing of all
774          * the dimm modules installed.
775          *-----------------------------------------------------------------*/
776         /* loop through all the DIMM slots on the board */
777         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
778                 /* If a dimm is installed in a particular slot ... */
779                 if (dimm_ranks[dimm_num]) {
780                         unsigned long ps;
781
782                         /* tWTR */
783                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
784                         t_wtr_ps = max(t_wtr_ps, ps);
785                         /* tRFC */
786                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
787                         spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
788                         ps += 256000 * (spd_40 & 0x01);
789                         switch ((spd_40 & 0x0E) >> 1) {
790                         case 0x1:
791                                 ps += 250;
792                                 break;
793                         case 0x2:
794                                 ps += 333;
795                                 break;
796                         case 0x3:
797                                 ps += 500;
798                                 break;
799                         case 0x4:
800                                 ps += 667;
801                                 break;
802                         case 0x5:
803                                 ps += 750;
804                                 break;
805                         }
806                         t_rfc_ps = max(t_rfc_ps, ps);
807                 }
808         }
809         debug("t_wtr_ps = %ld\n", t_wtr_ps);
810         t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
811         debug("t_rfc_ps = %ld\n", t_rfc_ps);
812         t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
813         mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
814                 DDR0_06_TRFC_ENCODE(t_rfc_clk));
815 }
816
817 static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
818 {
819         unsigned long csmap;
820
821         if (2 == ranks) {
822                 /* Both chip selects in use */
823                 csmap = 0x03;
824         } else {
825                 /* One chip select in use */
826                 csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
827         }
828         mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
829                 DDR0_10_CS_MAP_ENCODE(csmap) |
830                 DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
831 }
832
833 static void program_ddr0_11(unsigned long sdram_freq)
834 {
835         unsigned long const t_xsnr_ps = 200000; /* 200 ns */
836         unsigned long t_xsnr_clk;
837
838         debug("t_xsnr_ps = %ld\n", t_xsnr_ps);
839         t_xsnr_clk =
840             (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
841         mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
842                 DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
843 }
844
845 static void program_ddr0_22(unsigned long dimm_ranks[],
846                             unsigned char const iic0_dimm_addr[],
847                             unsigned long num_dimm_banks, unsigned long width)
848 {
849 #if defined(CONFIG_DDR_ECC)
850         unsigned long dimm_num;
851         unsigned long ecc_available = width >= 64;
852         u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
853             DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
854             DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
855
856         /* loop through all the DIMM slots on the board */
857         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
858                 /* If a dimm is installed in a particular slot ... */
859                 if (dimm_ranks[dimm_num]) {
860                         /* Check for ECC */
861                         if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
862                                   0x02)) {
863                                 ecc_available = false;
864                         }
865                 }
866         }
867         if (ecc_available) {
868                 debug("ECC found on all DIMMs present\n");
869                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
870         } else {
871                 debug("ECC not found on some or all DIMMs present\n");
872                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
873         }
874 #else
875         mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
876                 DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
877                 DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
878                 DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
879 #endif /* defined(CONFIG_DDR_ECC) */
880 }
881
882 static void program_ddr0_24(unsigned long ranks)
883 {
884         u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
885             DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
886
887         if (2 == ranks) {
888                 /* Both chip selects in use */
889                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
890                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
891         } else {
892                 /* One chip select in use */
893                 /* One of the two fields added to ddr0_24 is a "don't care" */
894                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
895                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
896         }
897         mtsdram(DDR0_24, ddr0_24);
898 }
899
900 static void program_ddr0_26(unsigned long sdram_freq)
901 {
902         unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
903         /* TODO: check definition of tRAS_MAX */
904         unsigned long const t_ras_max_ps = 9 * t_ref_ps;
905         unsigned long t_ras_max_clk;
906         unsigned long t_ref_clk;
907
908         /* Round down t_ras_max_clk and t_ref_clk */
909         debug("t_ras_max_ps = %ld\n", t_ras_max_ps);
910         t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
911         debug("t_ref_ps     = %ld\n", t_ref_ps);
912         t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
913         mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
914                 DDR0_26_TREF_ENCODE(t_ref_clk));
915 }
916
917 static void program_ddr0_27(unsigned long sdram_freq)
918 {
919         unsigned long const t_init_ps = 200000000;      /* 200 us. init */
920         unsigned long t_init_clk;
921
922         debug("t_init_ps = %ld\n", t_init_ps);
923         t_init_clk =
924             (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
925         mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
926                 DDR0_27_TINIT_ENCODE(t_init_clk));
927 }
928
929 static void program_ddr0_43(unsigned long dimm_ranks[],
930                             unsigned char const iic0_dimm_addr[],
931                             unsigned long num_dimm_banks,
932                             unsigned long sdram_freq,
933                             unsigned long cols, unsigned long banks)
934 {
935         unsigned long dimm_num;
936         unsigned long t_wr_ps = 0;
937         unsigned long t_wr_clk;
938         u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
939             DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
940             DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
941
942         /*------------------------------------------------------------------
943          * Handle the timing.  We need to find the worst case timing of all
944          * the dimm modules installed.
945          *-----------------------------------------------------------------*/
946         /* loop through all the DIMM slots on the board */
947         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
948                 /* If a dimm is installed in a particular slot ... */
949                 if (dimm_ranks[dimm_num]) {
950                         unsigned long ps;
951
952                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
953                         t_wr_ps = max(t_wr_ps, ps);
954                 }
955         }
956         debug("t_wr_ps = %ld\n", t_wr_ps);
957         t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
958         mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
959 }
960
961 static void program_ddr0_44(unsigned long dimm_ranks[],
962                             unsigned char const iic0_dimm_addr[],
963                             unsigned long num_dimm_banks,
964                             unsigned long sdram_freq)
965 {
966         unsigned long dimm_num;
967         unsigned long t_rcd_ps = 0;
968         unsigned long t_rcd_clk;
969
970         /*------------------------------------------------------------------
971          * Handle the timing.  We need to find the worst case timing of all
972          * the dimm modules installed.
973          *-----------------------------------------------------------------*/
974         /* loop through all the DIMM slots on the board */
975         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
976                 /* If a dimm is installed in a particular slot ... */
977                 if (dimm_ranks[dimm_num]) {
978                         unsigned long ps;
979
980                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
981                         t_rcd_ps = max(t_rcd_ps, ps);
982                 }
983         }
984         debug("t_rcd_ps = %ld\n", t_rcd_ps);
985         t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
986         mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
987 }
988
989 /*-----------------------------------------------------------------------------+
990  * initdram.  Initializes the 440EPx/GPx DDR SDRAM controller.
991  * Note: This routine runs from flash with a stack set up in the chip's
992  * sram space.  It is important that the routine does not require .sbss, .bss or
993  * .data sections.  It also cannot call routines that require these sections.
994  *-----------------------------------------------------------------------------*/
995 /*-----------------------------------------------------------------------------
996  * Function:     initdram
997  * Description:  Configures SDRAM memory banks for DDR operation.
998  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
999  *               via the IIC bus and then configures the DDR SDRAM memory
1000  *               banks appropriately. If Auto Memory Configuration is
1001  *               not used, it is assumed that no DIMM is plugged
1002  *-----------------------------------------------------------------------------*/
1003 int initdram(void)
1004 {
1005         unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
1006         unsigned long dimm_ranks[MAXDIMMS];
1007         unsigned long ranks;
1008         unsigned long rows;
1009         unsigned long banks;
1010         unsigned long cols;
1011         unsigned long width;
1012         unsigned long const sdram_freq = get_bus_freq(0);
1013         unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr);    /* on board dimm banks */
1014         unsigned long cas_latency = 0;  /* to quiet initialization warning */
1015         unsigned long dram_size;
1016
1017         debug("\nEntering initdram()\n");
1018
1019         /*------------------------------------------------------------------
1020          * Stop the DDR-SDRAM controller.
1021          *-----------------------------------------------------------------*/
1022         mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
1023
1024         /*
1025          * Make sure I2C controller is initialized
1026          * before continuing.
1027          */
1028         /* switch to correct I2C bus */
1029         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
1030
1031         /*------------------------------------------------------------------
1032          * Clear out the serial presence detect buffers.
1033          * Perform IIC reads from the dimm.  Fill in the spds.
1034          * Check to see if the dimm slots are populated
1035          *-----------------------------------------------------------------*/
1036         get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
1037
1038         /*------------------------------------------------------------------
1039          * Check the frequency supported for the dimms plugged.
1040          *-----------------------------------------------------------------*/
1041         check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1042
1043         /*------------------------------------------------------------------
1044          * Check and get size information.
1045          *-----------------------------------------------------------------*/
1046         get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
1047                       &cols, &width);
1048
1049         /*------------------------------------------------------------------
1050          * Check the voltage type for the dimms plugged.
1051          *-----------------------------------------------------------------*/
1052         check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
1053
1054         /*------------------------------------------------------------------
1055          * Program registers for SDRAM controller.
1056          *-----------------------------------------------------------------*/
1057         mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
1058                 DDR0_00_DLL_START_POINT_DECODE(0x0A));
1059
1060         mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
1061                 DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
1062                 DDR0_01_INT_MASK_ENCODE(0xFF));
1063
1064         program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1065                         rows, &cas_latency);
1066
1067         program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1068
1069         program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1070
1071         program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1072
1073         /*
1074          * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
1075          * board SDRAM, but may be overly conservative.
1076          */
1077         mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
1078                 DDR0_07_TFAW_ENCODE(13) |
1079                 DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
1080                 DDR0_07_AREFRESH_ENCODE(0));
1081
1082         mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
1083                 DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
1084                 DDR0_08_DDRII_ENCODE(1));
1085
1086         mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
1087                 DDR0_09_RTT_0_ENCODE(0x1) |
1088                 DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
1089                 DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
1090
1091         program_ddr0_10(dimm_ranks, ranks);
1092
1093         program_ddr0_11(sdram_freq);
1094
1095         mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
1096
1097         mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
1098                 DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
1099                 DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
1100
1101         mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
1102
1103         mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
1104                 DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
1105                 DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
1106                 DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
1107
1108         mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
1109                 DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
1110                 DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
1111                 DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
1112
1113         mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
1114                 DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
1115                 DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
1116                 DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
1117
1118         mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
1119                 DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
1120                 DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
1121                 DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
1122
1123         program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
1124
1125         mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
1126                 DDR0_23_FWC_ENCODE(0));
1127
1128         program_ddr0_24(ranks);
1129
1130         program_ddr0_26(sdram_freq);
1131
1132         program_ddr0_27(sdram_freq);
1133
1134         mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
1135                 DDR0_28_EMRS2_DATA_ENCODE(0x0000));
1136
1137         mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
1138
1139         mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
1140                 DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
1141
1142         program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1143                         cols, banks);
1144
1145         program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1146
1147         denali_sdram_register_dump();
1148
1149         dram_size = (width >= 64) ? 8 : 4;
1150         dram_size *= 1 << cols;
1151         dram_size *= banks;
1152         dram_size *= 1 << rows;
1153         dram_size *= ranks;
1154         debug("dram_size = %lu\n", dram_size);
1155
1156         /* Start the SDRAM controller */
1157         mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
1158         denali_wait_for_dlllock();
1159
1160 #if defined(CONFIG_DDR_DATA_EYE)
1161         /*
1162          * Map the first 1 MiB of memory in the TLB, and perform the data eye
1163          * search.
1164          */
1165         program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
1166         denali_core_search_data_eye();
1167         denali_sdram_register_dump();
1168         remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
1169 #endif
1170
1171 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
1172         program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
1173         sync();
1174         /* Zero the memory */
1175         debug("Zeroing SDRAM...");
1176 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
1177         dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1178 #else
1179 #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
1180 #endif
1181         /* Write modified dcache lines back to memory */
1182         clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1183         debug("Completed\n");
1184         sync();
1185         remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
1186
1187 #if defined(CONFIG_DDR_ECC)
1188         /*
1189          * If ECC is enabled, clear and enable interrupts
1190          */
1191         if (is_ecc_enabled()) {
1192                 u32 val;
1193
1194                 sync();
1195                 /* Clear error status */
1196                 mfsdram(DDR0_00, val);
1197                 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
1198                 /* Set 'int_mask' parameter to functionnal value */
1199                 mfsdram(DDR0_01, val);
1200                 mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
1201                         DDR0_01_INT_MASK_ALL_OFF);
1202 #if defined(CONFIG_DDR_DATA_EYE)
1203                 /*
1204                  * Running denali_core_search_data_eye() when ECC is enabled
1205                  * causes non-ECC machine checks.  This clears them.
1206                  */
1207                 print_mcsr();
1208                 mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
1209                 print_mcsr();
1210 #endif
1211                 sync();
1212         }
1213 #endif /* defined(CONFIG_DDR_ECC) */
1214 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
1215
1216         program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
1217         gd->ram_size = dram_size;
1218
1219         return 0;
1220 }
1221
1222 void board_add_ram_info(int use_default)
1223 {
1224         u32 val;
1225
1226         printf(" (ECC");
1227         if (!is_ecc_enabled()) {
1228                 printf(" not");
1229         }
1230         printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
1231
1232         mfsdram(DDR0_03, val);
1233         printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
1234 }
1235 #endif /* CONFIG_SPD_EEPROM */