2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
4 * File Name: 405gp_pci.c
6 * Function: Initialization code for the 405GP PCI Configuration regs.
12 * Date Description of Change BY
13 * --------- --------------------- ---
14 * 09-Sep-98 Created MCG
15 * 02-Nov-98 Removed External arbiter selected message JWB
16 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
17 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
18 * from (0 to n) to (1 to n).
19 * 17-May-99 Port to Walnut JWB
20 * 17-Jun-99 Updated for VGA support JWB
21 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
22 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
23 * target latency timer values are not supported).
24 * Should be fixed in pass 2.
25 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
26 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
27 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
28 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
29 * really required after a reset since PMMxMAs are already
30 * disabled but is a good practice nonetheless. JWB
31 * 12-Jun-01 stefan.roese@esd-electronics.com
32 * - PCI host/adapter handling reworked
33 * 09-Jul-01 stefan.roese@esd-electronics.com
34 * - PCI host now configures from device 0 (not 1) to max_dev,
35 * (host configures itself)
36 * - On CPCI-405 pci base address and size is generated from
37 * SDRAM and FLASH size (CFG regs not used anymore)
38 * - Some minor changes for CPCI-405-A (adapter version)
39 * 14-Sep-01 stefan.roese@esd-electronics.com
40 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
41 * 28-Sep-01 stefan.roese@esd-electronics.com
42 * - Changed pci master configuration for linux compatibility
43 * (no need for bios_fixup() anymore)
44 * 26-Feb-02 stefan.roese@esd-electronics.com
45 * - Bug fixed in pci configuration (Andrew May)
46 * - Removed pci class code init for CPCI405 board
47 * 15-May-02 stefan.roese@esd-electronics.com
48 * - New vga device handling
49 * 29-May-02 stefan.roese@esd-electronics.com
50 * - PCI class code init added (if defined)
51 *----------------------------------------------------------------------------*/
55 #include <asm/4xx_pci.h>
56 #include <asm/processor.h>
62 DECLARE_GLOBAL_DATA_PTR;
64 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
69 * Board-specific pci initialization
70 * Platform code can reimplement pci_pre_init() if needed
72 int __pci_pre_init(struct pci_controller *hose)
74 #if defined(CONFIG_405EP)
76 * Enable the internal PCI arbiter by default.
78 * On 405EP CPUs the internal arbiter can be controlled
79 * by the I2C strapping EEPROM. If you want to do so
80 * or if you want to disable the arbiter pci_pre_init()
81 * must be reimplemented without enabling the arbiter.
82 * The arbiter is enabled in this place because of
83 * compatibility reasons.
85 mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
86 #endif /* CONFIG_405EP */
90 int pci_pre_init(struct pci_controller *hose)
91 __attribute__((weak, alias("__pci_pre_init")));
93 int __is_pci_host(struct pci_controller *hose)
95 #if defined(CONFIG_405GP)
96 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
98 #elif defined (CONFIG_405EP)
99 if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
104 int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
106 /*-----------------------------------------------------------------------------+
107 * pci_init. Initializes the 405GP PCI Configuration regs.
108 *-----------------------------------------------------------------------------*/
109 void pci_405gp_init(struct pci_controller *hose)
114 unsigned short temp_short;
115 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
116 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
117 char *ptmla_str, *ptmms_str;
119 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
120 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
121 #if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
122 || defined(CONFIG_TARGET_MIP405T)
123 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
124 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
125 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
126 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
128 unsigned long pmmla[3] = {0x80000000, 0,0};
129 unsigned long pmmma[3] = {0xC0000001, 0,0};
130 unsigned long pmmpcila[3] = {0x80000000, 0,0};
131 unsigned long pmmpciha[3] = {0x00000000, 0,0};
133 #ifdef CONFIG_PCI_PNP
134 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
139 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
140 ptmla_str = getenv("ptm1la");
141 ptmms_str = getenv("ptm1ms");
142 if(NULL != ptmla_str && NULL != ptmms_str ) {
143 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
144 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
147 ptmla_str = getenv("ptm2la");
148 ptmms_str = getenv("ptm2ms");
149 if(NULL != ptmla_str && NULL != ptmms_str ) {
150 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
151 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
158 hose->first_busno = 0;
159 hose->last_busno = 0xff;
161 /* ISA/PCI I/O space */
162 pci_set_region(hose->regions + reg_num++,
169 pci_set_region(hose->regions + reg_num++,
181 if (!i) hose->pci_fb = hose->regions + reg_num;
183 pci_set_region(hose->regions + reg_num++,
184 ptmpcila[i], ptmla[i],
185 ~(ptmms[i] & 0xfffff000) + 1,
187 PCI_REGION_SYS_MEMORY);
190 /* PCI memory spaces */
194 pci_set_region(hose->regions + reg_num++,
195 pmmpcila[i], pmmla[i],
196 ~(pmmma[i] & 0xfffff000) + 1,
200 hose->region_count = reg_num;
202 pci_setup_indirect(hose,
207 pciauto_region_init(hose->pci_fb);
209 /* Let board change/modify hose & do initial checks */
210 if (pci_pre_init(hose) == 0) {
211 printf("PCI: Board-specific initialization failed.\n");
212 printf("PCI: Configuration aborted.\n");
216 pci_register_hose(hose);
218 /*--------------------------------------------------------------------------+
219 * 405GP PCI Master configuration.
220 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
221 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
222 * Use byte reversed out routines to handle endianess.
223 *--------------------------------------------------------------------------*/
224 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
225 out32r(PMM0LA, pmmla[0]);
226 out32r(PMM0PCILA, pmmpcila[0]);
227 out32r(PMM0PCIHA, pmmpciha[0]);
228 out32r(PMM0MA, pmmma[0]);
230 /*--------------------------------------------------------------------------+
231 * PMM1 is not used. Initialize them to zero.
232 *--------------------------------------------------------------------------*/
233 out32r(PMM1MA, (pmmma[1]&~0x1));
234 out32r(PMM1LA, pmmla[1]);
235 out32r(PMM1PCILA, pmmpcila[1]);
236 out32r(PMM1PCIHA, pmmpciha[1]);
237 out32r(PMM1MA, pmmma[1]);
239 /*--------------------------------------------------------------------------+
240 * PMM2 is not used. Initialize them to zero.
241 *--------------------------------------------------------------------------*/
242 out32r(PMM2MA, (pmmma[2]&~0x1));
243 out32r(PMM2LA, pmmla[2]);
244 out32r(PMM2PCILA, pmmpcila[2]);
245 out32r(PMM2PCIHA, pmmpciha[2]);
246 out32r(PMM2MA, pmmma[2]);
248 /*--------------------------------------------------------------------------+
249 * 405GP PCI Target configuration. (PTM1)
250 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
251 *--------------------------------------------------------------------------*/
252 out32r(PTM1LA, ptmla[0]); /* insert address */
253 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
254 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
256 /*--------------------------------------------------------------------------+
257 * 405GP PCI Target configuration. (PTM2)
258 *--------------------------------------------------------------------------*/
259 out32r(PTM2LA, ptmla[1]); /* insert address */
260 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
264 out32r(PTM2MS, 0x00000001); /* set enable bit */
265 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
266 out32r(PTM2MS, 0x00000000); /* disable */
270 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
274 * Insert Subsystem Vendor and Device ID
276 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
277 #ifdef CONFIG_CPCI405
278 if (is_pci_host(hose))
279 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
281 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
283 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
289 #ifdef CONFIG_SYS_PCI_CLASSCODE
290 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
291 #endif /* CONFIG_SYS_PCI_CLASSCODE */
293 /*--------------------------------------------------------------------------+
294 * If PCI speed = 66MHz, set 66MHz capable bit.
295 *--------------------------------------------------------------------------*/
296 if (bd->bi_pci_busfreq >= 66000000) {
297 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
298 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
301 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
302 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
303 if (is_pci_host(hose) ||
304 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
307 /*--------------------------------------------------------------------------+
308 * Write the 405GP PCI Configuration regs.
309 * Enable 405GP to be a master on the PCI bus (PMM).
310 * Enable 405GP to act as a PCI memory target (PTM).
311 *--------------------------------------------------------------------------*/
312 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
313 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
314 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
318 #if defined(CONFIG_405EP)
320 * on ppc405ep vendor/device id is not set
321 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
322 * are the correct values.
324 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
325 pci_write_config_word(PCIDEVID_405GP,
326 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
330 * Set HCE bit (Host Configuration Enabled)
332 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
333 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
335 #ifdef CONFIG_PCI_PNP
336 /*--------------------------------------------------------------------------+
337 * Scan the PCI bus and configure devices found.
338 *--------------------------------------------------------------------------*/
339 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
340 if (is_pci_host(hose) ||
341 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
344 #ifdef CONFIG_PCI_SCAN_SHOW
345 printf("PCI: Bus Dev VenId DevId Class Int\n");
347 hose->last_busno = pci_hose_scan(hose);
349 #endif /* CONFIG_PCI_PNP */
354 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
355 * be set as an Adapter.
357 * I (Andrew May) don't know what we should do here, but I don't want
358 * the auto setup of a PCI device disabling what is done pci_405gp_init
359 * as has happened before.
361 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
362 struct pci_config_table *entry)
365 printf("405gp_setup_bridge\n");
373 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
375 unsigned char int_line = 0xff;
378 * Write pci interrupt line register (cpci405 specific)
380 switch (PCI_DEV(dev) & 0x03)
396 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
399 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
400 struct pci_config_table *entry)
402 unsigned int cmdstat = 0;
404 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
406 /* always enable io space on vga boards */
407 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
408 cmdstat |= PCI_COMMAND_IO;
409 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
412 #if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
413 || defined(CONFIG_TARGET_MIP405T))
416 *As is these functs get called out of flash Not a horrible
417 *thing, but something to keep in mind. (no statics?)
419 static struct pci_config_table pci_405gp_config_table[] = {
420 /*if VendID is 0 it terminates the table search (ie Walnut)*/
421 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
422 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
423 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
425 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
426 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
428 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
429 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
434 static struct pci_controller hose = {
435 fixup_irq: pci_405gp_fixup_irq,
436 config_table: pci_405gp_config_table,
439 void pci_init_board(void)
441 /*we want the ptrs to RAM not flash (ie don't use init list)*/
442 hose.fixup_irq = pci_405gp_fixup_irq;
443 hose.config_table = pci_405gp_config_table;
444 pci_405gp_init(&hose);
449 #endif /* CONFIG_405GP */
451 /*-----------------------------------------------------------------------------+
453 *-----------------------------------------------------------------------------*/
454 #if defined(CONFIG_440)
456 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
457 static struct pci_controller ppc440_hose = {0};
461 * This routine is called to determine if a pci scan should be
462 * performed. With various hardware environments (especially cPCI and
463 * PPMC) it's insufficient to depend on the state of the arbiter enable
464 * bit in the strap register, or generic host/adapter assumptions.
466 * Rather than hard-code a bad assumption in the general 440 code, the
467 * 440 pci code requires the board to decide at runtime.
469 * Return 0 for adapter mode, non-zero for host (monarch) mode.
471 * Weak default implementation: "Normal" boards implement the PCI
472 * host functionality. This can be overridden for PCI adapter boards.
474 int __is_pci_host(struct pci_controller *hose)
478 int is_pci_host(struct pci_controller *hose)
479 __attribute__((weak, alias("__is_pci_host")));
481 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
482 defined(CONFIG_440GR) || defined(CONFIG_440GRX)
484 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
488 * The bootstrap configuration provides default settings for the pci
489 * inbound map (PIM). But the bootstrap config choices are limited and
490 * may not be sufficient for a given board.
492 void __pci_target_init(struct pci_controller *hose)
495 * Set up Direct MMIO registers
499 * PowerPC440 EP PCI Master configuration.
500 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
501 * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
502 * Use byte reversed out routines to handle endianess.
503 * Make this region non-prefetchable.
505 /* PMM0 Mask/Attribute - disabled b4 setting */
506 out_le32((void *)PCIL0_PMM0MA, 0x00000000);
507 /* PMM0 Local Address */
508 out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
509 /* PMM0 PCI Low Address */
510 out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
511 /* PMM0 PCI High Address */
512 out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
513 /* 512M + No prefetching, and enable region */
514 out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
516 /* PMM1 Mask/Attribute - disabled b4 setting */
517 out_le32((void *)PCIL0_PMM1MA, 0x00000000);
518 /* PMM1 Local Address */
519 out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
520 /* PMM1 PCI Low Address */
521 out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
522 /* PMM1 PCI High Address */
523 out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
524 /* 512M + No prefetching, and enable region */
525 out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
527 out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
528 out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
529 out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
530 out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
533 * Set up Configuration registers
536 /* Program the board's subsystem id/vendor id */
537 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
538 CONFIG_SYS_PCI_SUBSYS_VENDORID);
539 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
541 /* Configure command register as bus master */
542 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
544 /* 240nS PCI clock */
545 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
547 /* No error reporting */
548 pci_write_config_word(0, PCI_ERREN, 0);
550 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
552 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
557 * This routine is called just prior to registering the hose and gives
558 * the board the opportunity to check things. Returning a value of zero
559 * indicates that things are bad & PCI initialization should be aborted.
561 * Different boards may wish to customize the pci controller structure
562 * (add regions, override default access routines, etc) or perform
563 * certain pre-initialization actions.
566 int __pci_pre_init(struct pci_controller *hose)
571 * Set priority for all PLB3 devices to 0.
572 * Set PLB3 arbiter to fair mode.
574 mfsdr(SDR0_AMP1, reg);
575 mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
576 reg = mfdcr(PLB3A0_ACR);
577 mtdcr(PLB3A0_ACR, reg | 0x80000000);
580 * Set priority for all PLB4 devices to 0.
582 mfsdr(SDR0_AMP0, reg);
583 mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
584 reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
585 mtdcr(PLB4A0_ACR, reg);
588 * Set Nebula PLB4 arbiter to fair mode.
591 reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
592 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
593 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
594 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
595 mtdcr(PLB4A0_ACR, reg);
598 reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
599 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
600 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
601 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
602 mtdcr(PLB4A1_ACR, reg);
604 #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
605 hose->fixup_irq = board_pci_fixup_irq;
611 #else /* defined(CONFIG_440EP) ... */
613 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
614 void __pci_target_init(struct pci_controller * hose)
619 out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
620 out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
621 out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
622 out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
625 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
626 * strapping options do not support sizes such as 128/256 MB.
628 out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
629 out_le32((void *)PCIL0_PIM0LAH, 0);
630 out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
631 out_le32((void *)PCIL0_BAR0, 0);
634 * Program the board's subsystem id/vendor id
636 out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
637 out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
639 out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
642 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
644 int __pci_pre_init(struct pci_controller *hose)
647 * This board is always configured as the host & requires the
648 * PCI arbiter to be enabled.
650 if (!pci_arbiter_enabled()) {
651 printf("PCI: PCI Arbiter disabled!\n");
658 #endif /* defined(CONFIG_440EP) ... */
660 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
661 void pci_target_init(struct pci_controller * hose)
662 __attribute__((weak, alias("__pci_target_init")));
663 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
665 int pci_pre_init(struct pci_controller *hose)
666 __attribute__((weak, alias("__pci_pre_init")));
668 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
669 void __pci_master_init(struct pci_controller *hose)
674 * Write the PowerPC440 EP PCI Configuration regs.
675 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
676 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
678 pci_read_config_word(0, PCI_COMMAND, ®);
679 pci_write_config_word(0, PCI_COMMAND, reg |
680 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
682 void pci_master_init(struct pci_controller *hose)
683 __attribute__((weak, alias("__pci_master_init")));
684 #endif /* CONFIG_SYS_PCI_MASTER_INIT */
686 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
687 static int pci_440_init (struct pci_controller *hose)
691 #ifndef CONFIG_DISABLE_PISE_TEST
692 /*--------------------------------------------------------------------------+
693 * The PCI initialization sequence enable bit must be set ... if not abort
694 * pci setup since updating the bit requires chip reset.
695 *--------------------------------------------------------------------------*/
696 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
699 mfsdr(SDR0_SDSTP1,strap);
700 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
701 printf("PCI: SDR0_STRP1[PISE] not set.\n");
702 printf("PCI: Configuration aborted.\n");
705 #elif defined(CONFIG_440GP)
708 strap = mfdcr(CPC0_STRP1);
709 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
710 printf("PCI: CPC0_STRP1[PISE] not set.\n");
711 printf("PCI: Configuration aborted.\n");
715 #endif /* CONFIG_DISABLE_PISE_TEST */
717 /*--------------------------------------------------------------------------+
718 * PCI controller init
719 *--------------------------------------------------------------------------*/
720 hose->first_busno = 0;
721 hose->last_busno = 0;
724 pci_set_region(hose->regions + reg_num++,
730 /* PCI memory space */
731 pci_set_region(hose->regions + reg_num++,
732 CONFIG_SYS_PCI_TARGBASE,
733 CONFIG_SYS_PCI_MEMBASE,
734 #ifdef CONFIG_SYS_PCI_MEMSIZE
735 CONFIG_SYS_PCI_MEMSIZE,
741 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
742 defined(CONFIG_PCI_SYS_MEM_SIZE)
743 /* System memory space */
744 pci_set_region(hose->regions + reg_num++,
745 CONFIG_PCI_SYS_MEM_BUS,
746 CONFIG_PCI_SYS_MEM_PHYS,
747 CONFIG_PCI_SYS_MEM_SIZE,
748 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
751 hose->region_count = reg_num;
753 pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
755 /* Let board change/modify hose & do initial checks */
756 if (pci_pre_init(hose) == 0) {
757 printf("PCI: Board-specific initialization failed.\n");
758 printf("PCI: Configuration aborted.\n");
762 pci_register_hose( hose );
764 /*--------------------------------------------------------------------------+
766 *--------------------------------------------------------------------------*/
767 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
768 pci_target_init(hose); /* Let board setup pci target */
770 out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
771 out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
772 out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
775 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
776 defined(CONFIG_460EX) || defined(CONFIG_460GT)
777 out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
778 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
779 #elif defined(PCIL0_BRDGOPT1)
780 out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
781 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
784 /*--------------------------------------------------------------------------+
785 * PCI master init: default is one 256MB region for PCI memory:
786 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
787 *--------------------------------------------------------------------------*/
788 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
789 pci_master_init(hose); /* Let board setup pci master */
791 out32r( PCIL0_POM0SA, 0 ); /* disable */
792 out32r( PCIL0_POM1SA, 0 ); /* disable */
793 out32r( PCIL0_POM2SA, 0 ); /* disable */
794 #if defined(CONFIG_440SPE)
795 out32r( PCIL0_POM0LAL, 0x10000000 );
796 out32r( PCIL0_POM0LAH, 0x0000000c );
797 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
798 out32r( PCIL0_POM0LAL, 0x20000000 );
799 out32r( PCIL0_POM0LAH, 0x0000000c );
801 out32r( PCIL0_POM0LAL, 0x00000000 );
802 out32r( PCIL0_POM0LAH, 0x00000003 );
804 out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
805 out32r( PCIL0_POM0PCIAH, 0x00000000 );
806 out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
807 out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
810 /*--------------------------------------------------------------------------+
811 * PCI host configuration -- we don't make any assumptions here ... the
812 * _board_must_indicate_ what to do -- there's just too many runtime
813 * scenarios in environments like cPCI, PPMC, etc. to make a determination
814 * based on hard-coded values or state of arbiter enable.
815 *--------------------------------------------------------------------------*/
816 if (is_pci_host(hose)) {
817 #ifdef CONFIG_PCI_SCAN_SHOW
818 printf("PCI: Bus Dev VenId DevId Class Int\n");
820 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
821 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
822 out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
824 hose->last_busno = pci_hose_scan(hose);
826 return hose->last_busno;
830 void pci_init_board(void)
835 * Only init PCI when either master or target functionality
838 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
839 busno = pci_440_init(&ppc440_hose);
843 #if (defined(CONFIG_440SPE) || \
844 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
845 !defined(CONFIG_PCI_DISABLE_PCIE)
846 pcie_setup_hoses(busno + 1);
850 #endif /* CONFIG_440 */
852 #if defined(CONFIG_405EX)
853 void pci_init_board(void)
855 #ifdef CONFIG_PCI_SCAN_SHOW
856 printf("PCI: Bus Dev VenId DevId Class Int\n");
860 #endif /* CONFIG_405EX */
862 #endif /* CONFIG_PCI */