2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
4 * File Name: 405gp_pci.c
6 * Function: Initialization code for the 405GP PCI Configuration regs.
12 * Date Description of Change BY
13 * --------- --------------------- ---
14 * 09-Sep-98 Created MCG
15 * 02-Nov-98 Removed External arbiter selected message JWB
16 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
17 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
18 * from (0 to n) to (1 to n).
19 * 17-May-99 Port to Walnut JWB
20 * 17-Jun-99 Updated for VGA support JWB
21 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
22 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
23 * target latency timer values are not supported).
24 * Should be fixed in pass 2.
25 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
26 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
27 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
28 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
29 * really required after a reset since PMMxMAs are already
30 * disabled but is a good practice nonetheless. JWB
31 * 12-Jun-01 stefan.roese@esd-electronics.com
32 * - PCI host/adapter handling reworked
33 * 09-Jul-01 stefan.roese@esd-electronics.com
34 * - PCI host now configures from device 0 (not 1) to max_dev,
35 * (host configures itself)
36 * - On CPCI-405 pci base address and size is generated from
37 * SDRAM and FLASH size (CFG regs not used anymore)
38 * - Some minor changes for CPCI-405-A (adapter version)
39 * 14-Sep-01 stefan.roese@esd-electronics.com
40 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
41 * 28-Sep-01 stefan.roese@esd-electronics.com
42 * - Changed pci master configuration for linux compatibility
43 * (no need for bios_fixup() anymore)
44 * 26-Feb-02 stefan.roese@esd-electronics.com
45 * - Bug fixed in pci configuration (Andrew May)
46 * - Removed pci class code init for CPCI405 board
47 * 15-May-02 stefan.roese@esd-electronics.com
48 * - New vga device handling
49 * 29-May-02 stefan.roese@esd-electronics.com
50 * - PCI class code init added (if defined)
51 *----------------------------------------------------------------------------*/
55 #include <asm/4xx_pci.h>
56 #include <asm/processor.h>
62 DECLARE_GLOBAL_DATA_PTR;
64 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
66 #if defined(CONFIG_PMC405)
67 ushort pmc405_pci_subsys_deviceid(void);
73 * Board-specific pci initialization
74 * Platform code can reimplement pci_pre_init() if needed
76 int __pci_pre_init(struct pci_controller *hose)
78 #if defined(CONFIG_405EP)
80 * Enable the internal PCI arbiter by default.
82 * On 405EP CPUs the internal arbiter can be controlled
83 * by the I2C strapping EEPROM. If you want to do so
84 * or if you want to disable the arbiter pci_pre_init()
85 * must be reimplemented without enabling the arbiter.
86 * The arbiter is enabled in this place because of
87 * compatibility reasons.
89 mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
90 #endif /* CONFIG_405EP */
94 int pci_pre_init(struct pci_controller *hose)
95 __attribute__((weak, alias("__pci_pre_init")));
97 int __is_pci_host(struct pci_controller *hose)
99 #if defined(CONFIG_405GP)
100 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
102 #elif defined (CONFIG_405EP)
103 if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
108 int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
110 /*-----------------------------------------------------------------------------+
111 * pci_init. Initializes the 405GP PCI Configuration regs.
112 *-----------------------------------------------------------------------------*/
113 void pci_405gp_init(struct pci_controller *hose)
118 unsigned short temp_short;
119 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
120 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
121 char *ptmla_str, *ptmms_str;
123 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
124 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
125 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
126 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
127 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
128 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
129 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
131 unsigned long pmmla[3] = {0x80000000, 0,0};
132 unsigned long pmmma[3] = {0xC0000001, 0,0};
133 unsigned long pmmpcila[3] = {0x80000000, 0,0};
134 unsigned long pmmpciha[3] = {0x00000000, 0,0};
136 #ifdef CONFIG_PCI_PNP
137 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
142 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
143 ptmla_str = getenv("ptm1la");
144 ptmms_str = getenv("ptm1ms");
145 if(NULL != ptmla_str && NULL != ptmms_str ) {
146 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
147 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
150 ptmla_str = getenv("ptm2la");
151 ptmms_str = getenv("ptm2ms");
152 if(NULL != ptmla_str && NULL != ptmms_str ) {
153 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
154 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
161 hose->first_busno = 0;
162 hose->last_busno = 0xff;
164 /* ISA/PCI I/O space */
165 pci_set_region(hose->regions + reg_num++,
172 pci_set_region(hose->regions + reg_num++,
184 if (!i) hose->pci_fb = hose->regions + reg_num;
186 pci_set_region(hose->regions + reg_num++,
187 ptmpcila[i], ptmla[i],
188 ~(ptmms[i] & 0xfffff000) + 1,
190 PCI_REGION_SYS_MEMORY);
193 /* PCI memory spaces */
197 pci_set_region(hose->regions + reg_num++,
198 pmmpcila[i], pmmla[i],
199 ~(pmmma[i] & 0xfffff000) + 1,
203 hose->region_count = reg_num;
205 pci_setup_indirect(hose,
210 pciauto_region_init(hose->pci_fb);
212 /* Let board change/modify hose & do initial checks */
213 if (pci_pre_init(hose) == 0) {
214 printf("PCI: Board-specific initialization failed.\n");
215 printf("PCI: Configuration aborted.\n");
219 pci_register_hose(hose);
221 /*--------------------------------------------------------------------------+
222 * 405GP PCI Master configuration.
223 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
224 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
225 * Use byte reversed out routines to handle endianess.
226 *--------------------------------------------------------------------------*/
227 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
228 out32r(PMM0LA, pmmla[0]);
229 out32r(PMM0PCILA, pmmpcila[0]);
230 out32r(PMM0PCIHA, pmmpciha[0]);
231 out32r(PMM0MA, pmmma[0]);
233 /*--------------------------------------------------------------------------+
234 * PMM1 is not used. Initialize them to zero.
235 *--------------------------------------------------------------------------*/
236 out32r(PMM1MA, (pmmma[1]&~0x1));
237 out32r(PMM1LA, pmmla[1]);
238 out32r(PMM1PCILA, pmmpcila[1]);
239 out32r(PMM1PCIHA, pmmpciha[1]);
240 out32r(PMM1MA, pmmma[1]);
242 /*--------------------------------------------------------------------------+
243 * PMM2 is not used. Initialize them to zero.
244 *--------------------------------------------------------------------------*/
245 out32r(PMM2MA, (pmmma[2]&~0x1));
246 out32r(PMM2LA, pmmla[2]);
247 out32r(PMM2PCILA, pmmpcila[2]);
248 out32r(PMM2PCIHA, pmmpciha[2]);
249 out32r(PMM2MA, pmmma[2]);
251 /*--------------------------------------------------------------------------+
252 * 405GP PCI Target configuration. (PTM1)
253 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
254 *--------------------------------------------------------------------------*/
255 out32r(PTM1LA, ptmla[0]); /* insert address */
256 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
257 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
259 /*--------------------------------------------------------------------------+
260 * 405GP PCI Target configuration. (PTM2)
261 *--------------------------------------------------------------------------*/
262 out32r(PTM2LA, ptmla[1]); /* insert address */
263 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
267 out32r(PTM2MS, 0x00000001); /* set enable bit */
268 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
269 out32r(PTM2MS, 0x00000000); /* disable */
273 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
277 * Insert Subsystem Vendor and Device ID
279 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
280 #ifdef CONFIG_CPCI405
281 if (is_pci_host(hose))
282 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
284 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
286 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
292 #ifdef CONFIG_SYS_PCI_CLASSCODE
293 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
294 #endif /* CONFIG_SYS_PCI_CLASSCODE */
296 /*--------------------------------------------------------------------------+
297 * If PCI speed = 66MHz, set 66MHz capable bit.
298 *--------------------------------------------------------------------------*/
299 if (bd->bi_pci_busfreq >= 66000000) {
300 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
301 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
304 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
305 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
306 if (is_pci_host(hose) ||
307 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
310 /*--------------------------------------------------------------------------+
311 * Write the 405GP PCI Configuration regs.
312 * Enable 405GP to be a master on the PCI bus (PMM).
313 * Enable 405GP to act as a PCI memory target (PTM).
314 *--------------------------------------------------------------------------*/
315 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
316 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
317 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
321 #if defined(CONFIG_405EP)
323 * on ppc405ep vendor/device id is not set
324 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
325 * are the correct values.
327 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
328 pci_write_config_word(PCIDEVID_405GP,
329 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
333 * Set HCE bit (Host Configuration Enabled)
335 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
336 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
338 #ifdef CONFIG_PCI_PNP
339 /*--------------------------------------------------------------------------+
340 * Scan the PCI bus and configure devices found.
341 *--------------------------------------------------------------------------*/
342 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
343 if (is_pci_host(hose) ||
344 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
347 #ifdef CONFIG_PCI_SCAN_SHOW
348 printf("PCI: Bus Dev VenId DevId Class Int\n");
350 hose->last_busno = pci_hose_scan(hose);
352 #endif /* CONFIG_PCI_PNP */
357 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
358 * be set as an Adapter.
360 * I (Andrew May) don't know what we should do here, but I don't want
361 * the auto setup of a PCI device disabling what is done pci_405gp_init
362 * as has happened before.
364 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
365 struct pci_config_table *entry)
368 printf("405gp_setup_bridge\n");
376 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
378 unsigned char int_line = 0xff;
381 * Write pci interrupt line register (cpci405 specific)
383 switch (PCI_DEV(dev) & 0x03)
399 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
402 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
403 struct pci_config_table *entry)
405 unsigned int cmdstat = 0;
407 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
409 /* always enable io space on vga boards */
410 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
411 cmdstat |= PCI_COMMAND_IO;
412 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
415 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
418 *As is these functs get called out of flash Not a horrible
419 *thing, but something to keep in mind. (no statics?)
421 static struct pci_config_table pci_405gp_config_table[] = {
422 /*if VendID is 0 it terminates the table search (ie Walnut)*/
423 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
424 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
425 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
427 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
428 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
430 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
431 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
436 static struct pci_controller hose = {
437 fixup_irq: pci_405gp_fixup_irq,
438 config_table: pci_405gp_config_table,
441 void pci_init_board(void)
443 /*we want the ptrs to RAM not flash (ie don't use init list)*/
444 hose.fixup_irq = pci_405gp_fixup_irq;
445 hose.config_table = pci_405gp_config_table;
446 pci_405gp_init(&hose);
451 #endif /* CONFIG_405GP */
453 /*-----------------------------------------------------------------------------+
455 *-----------------------------------------------------------------------------*/
456 #if defined(CONFIG_440)
458 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
459 static struct pci_controller ppc440_hose = {0};
463 * This routine is called to determine if a pci scan should be
464 * performed. With various hardware environments (especially cPCI and
465 * PPMC) it's insufficient to depend on the state of the arbiter enable
466 * bit in the strap register, or generic host/adapter assumptions.
468 * Rather than hard-code a bad assumption in the general 440 code, the
469 * 440 pci code requires the board to decide at runtime.
471 * Return 0 for adapter mode, non-zero for host (monarch) mode.
473 * Weak default implementation: "Normal" boards implement the PCI
474 * host functionality. This can be overridden for PCI adapter boards.
476 int __is_pci_host(struct pci_controller *hose)
480 int is_pci_host(struct pci_controller *hose)
481 __attribute__((weak, alias("__is_pci_host")));
483 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
484 defined(CONFIG_440GR) || defined(CONFIG_440GRX)
486 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
490 * The bootstrap configuration provides default settings for the pci
491 * inbound map (PIM). But the bootstrap config choices are limited and
492 * may not be sufficient for a given board.
494 void __pci_target_init(struct pci_controller *hose)
497 * Set up Direct MMIO registers
501 * PowerPC440 EP PCI Master configuration.
502 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
503 * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
504 * Use byte reversed out routines to handle endianess.
505 * Make this region non-prefetchable.
507 /* PMM0 Mask/Attribute - disabled b4 setting */
508 out_le32((void *)PCIL0_PMM0MA, 0x00000000);
509 /* PMM0 Local Address */
510 out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
511 /* PMM0 PCI Low Address */
512 out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
513 /* PMM0 PCI High Address */
514 out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
515 /* 512M + No prefetching, and enable region */
516 out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
518 /* PMM1 Mask/Attribute - disabled b4 setting */
519 out_le32((void *)PCIL0_PMM1MA, 0x00000000);
520 /* PMM1 Local Address */
521 out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
522 /* PMM1 PCI Low Address */
523 out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
524 /* PMM1 PCI High Address */
525 out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
526 /* 512M + No prefetching, and enable region */
527 out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
529 out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
530 out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
531 out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
532 out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
535 * Set up Configuration registers
538 /* Program the board's subsystem id/vendor id */
539 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
540 CONFIG_SYS_PCI_SUBSYS_VENDORID);
541 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
543 /* Configure command register as bus master */
544 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
546 /* 240nS PCI clock */
547 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
549 /* No error reporting */
550 pci_write_config_word(0, PCI_ERREN, 0);
552 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
554 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
559 * This routine is called just prior to registering the hose and gives
560 * the board the opportunity to check things. Returning a value of zero
561 * indicates that things are bad & PCI initialization should be aborted.
563 * Different boards may wish to customize the pci controller structure
564 * (add regions, override default access routines, etc) or perform
565 * certain pre-initialization actions.
568 int __pci_pre_init(struct pci_controller *hose)
573 * Set priority for all PLB3 devices to 0.
574 * Set PLB3 arbiter to fair mode.
576 mfsdr(SDR0_AMP1, reg);
577 mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
578 reg = mfdcr(PLB3A0_ACR);
579 mtdcr(PLB3A0_ACR, reg | 0x80000000);
582 * Set priority for all PLB4 devices to 0.
584 mfsdr(SDR0_AMP0, reg);
585 mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
586 reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
587 mtdcr(PLB4A0_ACR, reg);
590 * Set Nebula PLB4 arbiter to fair mode.
593 reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
594 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
595 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
596 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
597 mtdcr(PLB4A0_ACR, reg);
600 reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
601 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
602 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
603 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
604 mtdcr(PLB4A1_ACR, reg);
606 #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
607 hose->fixup_irq = board_pci_fixup_irq;
613 #else /* defined(CONFIG_440EP) ... */
615 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
616 void __pci_target_init(struct pci_controller * hose)
621 out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
622 out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
623 out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
624 out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
627 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
628 * strapping options do not support sizes such as 128/256 MB.
630 out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
631 out_le32((void *)PCIL0_PIM0LAH, 0);
632 out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
633 out_le32((void *)PCIL0_BAR0, 0);
636 * Program the board's subsystem id/vendor id
638 out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
639 out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
641 out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
644 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
646 int __pci_pre_init(struct pci_controller *hose)
649 * This board is always configured as the host & requires the
650 * PCI arbiter to be enabled.
652 if (!pci_arbiter_enabled()) {
653 printf("PCI: PCI Arbiter disabled!\n");
660 #endif /* defined(CONFIG_440EP) ... */
662 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
663 void pci_target_init(struct pci_controller * hose)
664 __attribute__((weak, alias("__pci_target_init")));
665 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
667 int pci_pre_init(struct pci_controller *hose)
668 __attribute__((weak, alias("__pci_pre_init")));
670 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
671 void __pci_master_init(struct pci_controller *hose)
676 * Write the PowerPC440 EP PCI Configuration regs.
677 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
678 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
680 pci_read_config_word(0, PCI_COMMAND, ®);
681 pci_write_config_word(0, PCI_COMMAND, reg |
682 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
684 void pci_master_init(struct pci_controller *hose)
685 __attribute__((weak, alias("__pci_master_init")));
686 #endif /* CONFIG_SYS_PCI_MASTER_INIT */
688 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
689 static int pci_440_init (struct pci_controller *hose)
693 #ifndef CONFIG_DISABLE_PISE_TEST
694 /*--------------------------------------------------------------------------+
695 * The PCI initialization sequence enable bit must be set ... if not abort
696 * pci setup since updating the bit requires chip reset.
697 *--------------------------------------------------------------------------*/
698 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
701 mfsdr(SDR0_SDSTP1,strap);
702 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
703 printf("PCI: SDR0_STRP1[PISE] not set.\n");
704 printf("PCI: Configuration aborted.\n");
707 #elif defined(CONFIG_440GP)
710 strap = mfdcr(CPC0_STRP1);
711 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
712 printf("PCI: CPC0_STRP1[PISE] not set.\n");
713 printf("PCI: Configuration aborted.\n");
717 #endif /* CONFIG_DISABLE_PISE_TEST */
719 /*--------------------------------------------------------------------------+
720 * PCI controller init
721 *--------------------------------------------------------------------------*/
722 hose->first_busno = 0;
723 hose->last_busno = 0;
726 pci_set_region(hose->regions + reg_num++,
732 /* PCI memory space */
733 pci_set_region(hose->regions + reg_num++,
734 CONFIG_SYS_PCI_TARGBASE,
735 CONFIG_SYS_PCI_MEMBASE,
736 #ifdef CONFIG_SYS_PCI_MEMSIZE
737 CONFIG_SYS_PCI_MEMSIZE,
743 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
744 defined(CONFIG_PCI_SYS_MEM_SIZE)
745 /* System memory space */
746 pci_set_region(hose->regions + reg_num++,
747 CONFIG_PCI_SYS_MEM_BUS,
748 CONFIG_PCI_SYS_MEM_PHYS,
749 CONFIG_PCI_SYS_MEM_SIZE,
750 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
753 hose->region_count = reg_num;
755 pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
757 /* Let board change/modify hose & do initial checks */
758 if (pci_pre_init(hose) == 0) {
759 printf("PCI: Board-specific initialization failed.\n");
760 printf("PCI: Configuration aborted.\n");
764 pci_register_hose( hose );
766 /*--------------------------------------------------------------------------+
768 *--------------------------------------------------------------------------*/
769 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
770 pci_target_init(hose); /* Let board setup pci target */
772 out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
773 out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
774 out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
777 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
778 defined(CONFIG_460EX) || defined(CONFIG_460GT)
779 out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
780 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
781 #elif defined(PCIL0_BRDGOPT1)
782 out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
783 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
786 /*--------------------------------------------------------------------------+
787 * PCI master init: default is one 256MB region for PCI memory:
788 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
789 *--------------------------------------------------------------------------*/
790 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
791 pci_master_init(hose); /* Let board setup pci master */
793 out32r( PCIL0_POM0SA, 0 ); /* disable */
794 out32r( PCIL0_POM1SA, 0 ); /* disable */
795 out32r( PCIL0_POM2SA, 0 ); /* disable */
796 #if defined(CONFIG_440SPE)
797 out32r( PCIL0_POM0LAL, 0x10000000 );
798 out32r( PCIL0_POM0LAH, 0x0000000c );
799 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
800 out32r( PCIL0_POM0LAL, 0x20000000 );
801 out32r( PCIL0_POM0LAH, 0x0000000c );
803 out32r( PCIL0_POM0LAL, 0x00000000 );
804 out32r( PCIL0_POM0LAH, 0x00000003 );
806 out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
807 out32r( PCIL0_POM0PCIAH, 0x00000000 );
808 out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
809 out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
812 /*--------------------------------------------------------------------------+
813 * PCI host configuration -- we don't make any assumptions here ... the
814 * _board_must_indicate_ what to do -- there's just too many runtime
815 * scenarios in environments like cPCI, PPMC, etc. to make a determination
816 * based on hard-coded values or state of arbiter enable.
817 *--------------------------------------------------------------------------*/
818 if (is_pci_host(hose)) {
819 #ifdef CONFIG_PCI_SCAN_SHOW
820 printf("PCI: Bus Dev VenId DevId Class Int\n");
822 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
823 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
824 out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
826 hose->last_busno = pci_hose_scan(hose);
828 return hose->last_busno;
832 void pci_init_board(void)
837 * Only init PCI when either master or target functionality
840 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
841 busno = pci_440_init(&ppc440_hose);
845 #if (defined(CONFIG_440SPE) || \
846 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
847 !defined(CONFIG_PCI_DISABLE_PCIE)
848 pcie_setup_hoses(busno + 1);
852 #endif /* CONFIG_440 */
854 #if defined(CONFIG_405EX)
855 void pci_init_board(void)
857 #ifdef CONFIG_PCI_SCAN_SHOW
858 printf("PCI: Bus Dev VenId DevId Class Int\n");
862 #endif /* CONFIG_405EX */
864 #endif /* CONFIG_PCI */